Capacitor mismatch foreground calibration method suitable for SAR ADC

Abstract

The invention relates to a capacitor mismatch foreground calibration method suitable for an SARADC, and the method comprises the steps: S1, enabling an analog input signal, a random jitter signal and a dynamic element to be matched with each other, and jointly inputting the signals into a capacitive digital-to-analog converter; s2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing to obtain an output digital code; s3, calculating an evaluation value of the corresponding output digital code; s4, obtaining an error between the actual output value and the reference output value estimation value; s5, iterating the capacitance weight and the random signal according to the size of the error by utilizing an LMS (Least Mean Square) algorithm; and S6, continuously changing the capacitance weight and the random signal to enable the error to be within an allowable range, and obtaining more accurate output. According to the invention, no additional analog circuit needs to be added for capacitor mismatch calibration, and parameters such as the significant bit number and the spurious-free dynamic range of the ADC are obviously improved.

Description

Technical Field

[0001] The invention belongs to the technical field of digital-analog hybrid integrated circuit design, and in particular relates to a capacitance mismatch foreground digital calibration method applicable to a SAR ADC (successive approximation analog-to-digital converter). Background Art

[0002] As a bridge between analog and digital signals, analog-to-digital converters are widely used in communication radar, medical imaging, and audio processing. Among them, the successive approximation analog-to-digital converter (SAR ADC) is an ADC structure based on a binary search algorithm. It consists of an input sampling switch, a DAC array, a comparator, and a SAR digital control logic module. It has a simple structure and excellent energy efficiency, making it a mainstream architecture in the fields of medium speed, medium precision, and low power consumption. However, due to the limitations of chip manufacturing processes, DAC capacitors often have mismatch problems, which seriously affects the performance of SAR ADCs.

[0003] At present, the calibration technology for capacitor mismatch is mainly digital calibration technology. Among them, the calibration technology that performs an additional periodic calibration phase before the SAR ADC works normally is called foreground calibration. The least mean square error algorithm (LMS) is a common algorithm used for digital calibration of capacitor mismatch. The LMS circuit is equivalent to an adaptive filtering circuit, which continuously updates the weight coefficient of the filter so that the difference between the target signal and the filter output signal is infinitely reduced and approaches zero. The LMS algorithm is also called the stochastic gradient algorithm. Due to the difference in samples, the direction of each weight adjustment is also random, but overall, it is adjusted in the optimal direction. Using the LMS algorithm for mismatch calibration can effectively eliminate error terms and achieve rapid convergence.

[0004] However, although the foreground digital calibration has relatively small hardware overhead, the calibration process is mostly overly dependent on the input signal, the convergence speed is slow, which has a great impact on the conversion process of the SAR ADC and is not conducive to deep calibration. Therefore, it is necessary to propose a capacitor mismatch calibration method that does not require additional circuits and has a fast calibration convergence speed, which can not only realize calibration, but also achieve the effect of fast convergence, effectively improving the effective number of bits and spurious-free dynamic range of the SAR ADC. Summary of the invention

[0005] Aiming at the shortcomings of the existing capacitor array mismatch calibration technology, the present invention proposes a capacitor mismatch foreground digital calibration method for SAR ADC.

[0006] To achieve the above object, the technical solution adopted by the present invention is:

[0007] A capacitance mismatch foreground calibration method applicable to SAR ADC comprises the following steps:

[0008] S1, analog input signal, random jitter signal and dynamic element matching common input capacitor type digital-to-analog converter CDAC;

[0009] S2, compare the output of CDAC with the reference point through a comparator, and store the output digital code;

[0010] S3, calculating the evaluation value of the corresponding output digital code;

[0011] S4, calculating the error between the actual output value and the estimated reference output value;

[0012] S5, using the LMS algorithm to iterate the capacitance weight and the random signal according to the error size;

[0013] S6. Continuously change the capacitance weight and random signal to keep the error within the allowable range and obtain a more accurate output.

[0014] In one embodiment, S1 is specifically to set the analog input signal to zero, and to match the random jitter signal and the dynamic element and act on the capacitor array of CDAC at the same time, which is recorded as a random signal r(n), wherein the capacitor array includes a first capacitor array and a second capacitor array, the first capacitor array is a high M-bit quantization capacitor MSB, and the second capacitor array is a low (NM)-bit quantization capacitor LSB, wherein M is a positive integer not greater than N.

[0015] In one embodiment, S2 is specifically, from high to low, switching through the pre-charging phase and the charge redistribution phase in sequence, comparing the output point of the CDAC with the reference point through a comparator, switching the switch of the capacitor array according to the output of the comparator, performing successive approximation comparison, and storing the obtained digital output code.

[0016] In one embodiment, in S2, the switching process of the capacitor array includes:

[0017] The bottom plate of the capacitor array is connected to the input signal to be sampled, and the top plate of the capacitor array is grounded. When the sampling phase ends, the first comparison phase begins, starting from the highest-order capacitor of the MSB, and calibrating from high to low. The bottom plate of the highest-order capacitor connected to the reverse input of the comparator is switched to the power supply voltage VREF, and the bottom plates of the remaining capacitors are switched to the ground GND.

[0018] After the above switching operation is completed, the comparator starts to work. If the comparison result is negative, the voltage corresponding to the highest capacitor is switched to GND, and the voltage corresponding to the second highest capacitor is switched to VREF; if the comparison result is positive, the voltage corresponding to the highest capacitor remains unchanged, and the voltage corresponding to the second highest capacitor is switched to VREF;

[0019] Repeat the above comparison and switching operations until the last comparison result is output, and the entire successive approximation process is completed.

[0020] In one embodiment, the calculation formula of S3 is:

[0021]

[0022] in, is the actual output, W i (n) is the capacitance weight of the ith bit, D i (n) is the i-th output digital code.

[0023] In one embodiment, the calculation formula of S4 is:

[0024]

[0025] Among them, Error(n) is the error, is an estimate of the theoretical output value, V OUT is the output value.

[0026] In one embodiment, in S5, the iterative formulas of the capacitance weight and the random signal are respectively:

[0027]

[0028] r(n+1)=r(n)-μ r Error(n);

[0029] In the formula, μ W and μ r They are the weight convergence factor and random signal convergence factor in the LMS algorithm respectively.

[0030] In one embodiment, the W calculated by the iterative formula is i and r are updated to the next sampling conversion cycle, the preset values ​​of the capacitance weight and the size of the injected random signal can be continuously changed, and finally the Error is within the allowable error range.

[0031] In one embodiment, μ W The value of μ is 1 / 256, r The value range is 0.005~0.01.

[0032] The present invention has the following beneficial effects: the foreground digital calibration method for capacitor mismatch of the SAR ADC of the present invention converts the non-ideal characteristic of comparator offset into the expected output value in the LMS algorithm, and combines the jitter and dynamic element matching algorithms to increase the randomness of capacitor selection, so as to converge and optimize the capacitor weights from a global perspective. The calibration algorithm is completed before the normal conversion of the ADC, without adding additional analog circuits, and the calibration parameters can converge quickly, achieving a better calibration effect with a lower hardware overhead. After calibration, the overall effective number of bits and spurious-free dynamic range are significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0034] Figure 1 The present invention is a flowchart of a capacitance mismatch foreground calibration method applicable to a SAR ADC according to an embodiment of the present invention.

[0035] Figure 2 1 is a working principle diagram of a capacitance mismatch foreground calibration method for a SAR ADC according to an embodiment of the present invention.

[0036] Figure 3 It is a schematic diagram of the dynamic performance of SAR ADC before calibration.

[0037] Figure 4 It is a schematic diagram of the dynamic performance of the SAR ADC after calibration. DETAILED DESCRIPTION

[0038] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0039] like Figure 2As shown, the SAR ADC includes a sampling and holding circuit, an N-bit quantization capacitor array, a SAR logic, a comparator and a serial-to-parallel conversion circuit SR. The sampling and holding circuit is divided into two modes: tracking and holding. In the tracking mode, the rapidly changing analog input signal is sampled, and in the holding mode, the collected signal is maintained unchanged when the input signal is quantized. The N-bit quantization capacitor array is arranged from small to large according to the capacitance weight value, and is respectively the 0th to the N-1th quantization capacitor, and is divided into a first capacitor array and a second capacitor array. The first capacitor array is a high M-bit quantization capacitor (denoted as MSB), and the second capacitor array is a low (NM) bit quantization capacitor (denoted as LSB), where M is a positive integer not greater than N. The upper plate of the N-bit quantization capacitor array is connected in parallel as the output end of the capacitor array, connected to the reverse input end of the comparator, and in the direction away from the comparator, the number of capacitor bits in the first capacitor array and the second capacitor array of the capacitor array is increased in sequence. Among them, the lower plates of multiple capacitors in the first capacitor array are connected in parallel to the input signal, SAR logic, ground voltage GND or corresponding reference voltage VREF (generally power supply voltage); the lower plates of multiple capacitors in the second capacitor array are connected in parallel to the SAR logic, ground voltage GND or corresponding reference voltage VREF. SAR logic is used to control the capacitor switching during the conversion process. The comparator is used to compare the quantized value of the input signal with the reference output value. The positive input terminal of the comparator is grounded to the voltage GND. The input terminal of the SR circuit is connected to the output terminal of the comparator, and the output terminal of the SR circuit is connected to the output terminal of the ADC circuit.

[0040] In SAR ADC, ADC is divided into two working modes: calibration mode and normal working mode. The calibration mode is used to implement digital front-end calibration to obtain the optimal weight of N-bit capacitors; the normal conversion mode is used for normal sampling and quantization output. Different from the normal conversion mode, the calibration mode realizes the injection of disturbance by changing the connection mode of the capacitor switch of a certain bit in the capacitor array before sampling, and the quantized value of the disturbance is iterated through the calibration module LMS, so that the optimal weight is saved for calibration output in the normal conversion mode. The working process in the calibration mode is described in detail below.

[0041] like Figure 1 and 2 As shown, a capacitance mismatch foreground calibration method applicable to SAR ADC includes the following steps:

[0042] S1, analog input signal, random jitter signal and dynamic components match the common input capacitor type digital-to-analog converter CDAC.

[0043] Specifically, the analog input signal is set to zero, the ADC samples the input signal, and the input signal acts on the capacitive digital-to-analog converter (CDAC). At this time, the digital random dither signal (Dither) and dynamic element matching technology (Dynamice element matching, DEM) are simultaneously applied to the CDAC array, recorded as a random signal r(n), which is superimposed on the analog input signal to obtain a composite signal.

[0044] S2. Compare the output of CDAC with the reference point through a comparator and store the output digital code.

[0045] Specifically, from high to low, the pre-charging phase and the charge redistribution phase are switched in turn, and the output point of the CDAC is compared with the reference point through a comparator. The control module switches the switch of the capacitor array according to the output of the comparator, performs successive approximation comparison, and stores the obtained digital output code.

[0046] For the switching process of the capacitor array: the bottom plate of the capacitor array is connected to the sampled input signal, and the top plate of the capacitor array is grounded. When the sampling stage is over, the first comparison stage is entered. Starting from the highest-order capacitor of the high-M-bit quantization capacitor MSB, calibration is started from high to low. The bottom plate of the highest-order capacitor connected to the reverse input of the comparator is switched to VREF (generally the power supply voltage), and the bottom plates of the remaining capacitors are switched to GND. After the above switching operation is completed, the comparator starts working. If the comparison result is negative, the voltage corresponding to the highest-order capacitor is switched to GND, and the voltage corresponding to the second-highest-order capacitor is switched to VREF; if the comparison result is positive, the voltage corresponding to the highest-order capacitor remains unchanged, and the voltage corresponding to the second-highest-order capacitor is switched to VREF. Repeat the above comparison and switching operations until the last comparison result is output, and the entire successive approximation process is completed.

[0047] S3, calculate the evaluation value of the corresponding output digital code, and eliminate the influence of the random injection signal to obtain the output

[0048]

[0049] Where W i is the capacitance weight of the ith bit, D i Output digital code for the i-th bit;

[0050] When the effect of capacitor mismatch is ignored, the output value obtained should be the output with the non-ideal characteristics of comparator offset, denoted by X REF_OS is the theoretical output value, but the theoretical output value cannot be obtained by direct calculation or simulation, so the estimated value of the quantized theoretical output value is get:

[0051]

[0052] Where V OUT is the output value.

[0053] The calibration module specifically uses the LMS adaptive method, which includes three modules: error calculation, weight iterative calculation and disturbance iterative calculation.

[0054] S4. Calculate the error between the actual output value and the estimated reference output value.

[0055] Specifically, the quantized result of the injected disturbance is input into the error calculation module, and the error calculation module makes a difference between the actual output and the reference output value to obtain the error Error(n):

[0056]

[0057] Right now,

[0058] Ideally, the size of the Error should be zero, but non-ideal factors such as capacitor mismatch cause the actual result to be non-zero, so the Error needs to be further processed.

[0059] S5. Use the LMS algorithm to iterate the capacitance weight and the random signal according to the error size.

[0060] Specifically, the Error is placed in the weight iteration module and the perturbation iteration module of the LMS feedback loop. The non-zero Error drives the feedback loop to implement the adaptive LMS cycle. According to each error, it continuously iterates to obtain new weights and perturbation values, providing new parameters for the next error calculation. The weight iteration formula and perturbation iteration formula are:

[0061]

[0062] r(n+1)=r(n)-μ r Error(n);

[0063] Among them, μ W and μ r They are the weight convergence factor and random signal convergence factor in the LMS algorithm respectively.

[0064] S6. Continuously change the capacitance weight and random signal to keep the error within the allowable range and obtain a more accurate output.

[0065] Specifically, the W calculated by the iterative formula iand r are updated to the next sampling conversion cycle, the preset values ​​of the capacitance weight and the size of the injected random signal can be continuously changed; finally, Error is within the allowable error range (for example, Error ≤ VREF*(1 / 2) N ), that is, completing the capacitor mismatch front-end calibration to obtain a more accurate output.

[0066] After a certain number of iterations, when the error Error is within the allowable error range or after a certain number of iterations, the current weight is used as the weight after SAR ADC calibration. When the SAR ADC converts normally, the converted quantized value is added to the compensation calibration value, that is, the capacitor mismatch foreground calibration is completed, and finally a more accurate output is obtained after calibration.

[0067] The value of the convergence factor μ will affect the convergence speed of the LMS algorithm and the accuracy and steady-state error of the system after calibration. When the value of μ is large, the convergence time of the calibration algorithm will be faster, but the accuracy and steady-state error of the system will be affected. On the contrary, when the value of μ is small, the accuracy and steady-state error of the system will be improved, but the convergence time of the calibration algorithm will also increase significantly. Therefore, it is necessary to find a suitable convergence factor μ to strike a balance between the convergence speed of the LMS algorithm and the accuracy and steady-state of the system.

[0068] The simulation is performed with the convergence factor μ as a variable, and the average values ​​of ENOB and SFDR after multiple calibrations (for example, 100, 200 or 500 times) are taken as references. By analyzing the simulation results, it can be seen that when the convergence factor μ is large, the LMS algorithm does not converge. Even if the convergence is completed, the steady-state error generated by the weight still oscillates around the stable value seriously affects the calibration effect of the system. When the convergence factor μ meets the accuracy requirements, the SAR ADC after mismatch calibration can meet the required performance requirements. When the convergence factor μ is further reduced, the convergence step size of the SAR ADC increases significantly, but the performance improvement after calibration is limited. Based on the analysis of the simulation results, when μ W The value of μ is 1 / 256, r When the value range of is 0.005~0.01, the accuracy and convergence speed of the calibration method can be well compromised.

[0069] Figure 3 and 4 The dynamic performance of the SAR ADC before and after calibration is shown. The signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are important indicators for measuring the dynamic performance of the ADC. The effective number of bits (ENOB) refers to the resolution that the ADC can actually achieve after considering various noises and harmonics. Capacitor mismatch will introduce nonlinear errors in the actual conversion process of the SAR ADC, directly affecting the SFDR index and affecting the SNDR, thereby reducing the ENOB of the ADC. Figure 3 and Figure 4 It can be seen that the ENOB, SNDR and SFDR after calibration are greatly improved, and the capacitor mismatch calibration effect of SAR ADC is significantly improved.

[0070] The capacitor mismatch calibration method for SAR ADC proposed in the present invention combines DEM and pseudo-random jitter signals, and directly uses the CDAC array for calibration, without the need for additional capacitor overhead, and without the need to add additional analog circuits, thereby greatly reducing the circuit area and power consumption. The method evaluates the theoretical input voltage through the actual output digital code, and uses the LMS algorithm to continuously iteratively update the capacitor weight and random signal to minimize the error, thereby obtaining the actual weight of each capacitor and effectively correcting the capacitor mismatch. The invention achieves a better calibration effect with a lower hardware overhead, and improves the circuit's dynamic parameters such as the signal-to-noise distortion ratio and the spurious-free dynamic range.

[0071] The above shows and describes the basic principles, main features and application effects of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A capacitance mismatch foreground calibration method suitable for SARADC, characterized in that: The following steps are involved: S1, analog input signal, random jitter signal and dynamic element matching common input capacitor type digital-to-analog converter CDAC; S2, compare the output of CDAC with the reference point through a comparator, and store the output digital code; S3, calculating the evaluation value of the corresponding output digital code; S4, calculating the error between the actual output value and the estimated reference output value; S5, using the LMS algorithm to iterate the capacitance weight and the random signal according to the error size; S6. Continuously change the capacitance weight and random signal to keep the error within the allowable range and obtain a more accurate output.

2. The method according to claim 1, characterized in that Specifically, S1 sets the analog input signal to zero, matches the random jitter signal and the dynamic element, and acts on the capacitor array of CDAC at the same time, which is recorded as a random signal r(n), wherein the capacitor array includes a first capacitor array and a second capacitor array, the first capacitor array is a high M-bit quantization capacitor MSB, and the second capacitor array is a low (NM)-bit quantization capacitor LSB, wherein M is a positive integer not greater than N.

3. The method according to claim 2, characterized in that Specifically, S2 switches the pre-charging phase and the charge redistribution phase from high to low, compares the output point of the CDAC with the reference point through a comparator, switches the capacitor array according to the output of the comparator, performs successive approximation comparison, and stores the obtained digital output code.

4. The method according to claim 3, characterized in that In S2, the switching process of the capacitor array includes: The bottom plate of the capacitor array is connected to the input signal to be sampled, and the top plate of the capacitor array is grounded. When the sampling phase ends, the first comparison phase begins, starting from the highest-order capacitor of the MSB, and calibrating from high to low. The bottom plate of the highest-order capacitor connected to the reverse input of the comparator is switched to the power supply voltage VREF, and the bottom plates of the remaining capacitors are switched to the ground GND. After the above switching operation is completed, the comparator starts to work. If the comparison result is negative, the voltage corresponding to the highest capacitor is switched to GND, and the voltage corresponding to the second highest capacitor is switched to VREF; if the comparison result is positive, the voltage corresponding to the highest capacitor remains unchanged, and the voltage corresponding to the second highest capacitor is switched to VREF; Repeat the above comparison and switching operations until the last comparison result is output, and the entire successive approximation process is completed.

5. The method according to claim 4, characterized in that The calculation formula of S3 is: in, is the actual output, W i (n) is the capacitance weight of the ith bit, D i (n) is the i-th output digital code.

6. The method according to claim 5, characterized in that The calculation formula of S4 is: Among them, Error(n) is the error, is an estimate of the theoretical output value, V OUT is the output value.

7. The method according to claim 6, characterized in that In S5, the iterative formulas for capacitance weight and random signal are: r(n+1)=r(n)-μ r Error(n); In the formula, μ W and μ r They are the weight convergence factor and random signal convergence factor in the LMS algorithm respectively.

8. The method according to claim 7, characterized in that S6 is specifically: W calculated by the iterative formula i and r are updated to the next sampling conversion cycle, the preset values ​​of the capacitance weight and the size of the injected random signal can be continuously changed, and finally the Error is within the allowable error range.

9. The method according to claim 7, characterized in that: μ W The value of μ is 1 / 256, r The value range is 0.005~0.01.

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