The invention provides a low-dropout
linear regulator circuit with a high
power supply rejection ratio, and belongs to the field of analog circuit integration. The low-dropout
linear regulator circuitcomprises a bias module, an
error amplifier, a buffer and an output stage, wherein the bias module provides bias
voltage; a positive input end of the
error amplifier is connected to reference
voltage, a negative input end of the
error amplifier is connected to feedback
voltage, and an output end of the error
amplifier passes through the buffer and the output stage to be connected to an output endof an LDO; the buffer comprises an amplification stage, a high-pass filter and a
current source, and the amplification stage is connected between an input end and output end of the buffer; the
current source is connected between
power supply voltage and the output end of the buffer; the high-pass filter comprises a first NMOS
transistor, a first PMOS
transistor, a second PMOS
transistor and a first
capacitor, a grid
electrode of the first PMOS transistor is connected with the bias voltage, a source
electrode of the first PMOS transistor is connected with
power supply voltage and is connectedto a drain
electrode of the first PMOS transistor, a grid electrode of the second PMOS transistor and a grid electrode and drain electrode of the first NMOS transistor after passing through the firstcapacitor; a source electrode of the second PMOS transistor is connected with the output end of the buffer, and a drain electrode of the second PMOS transistor is connected with a source electrode ofthe first NMOS transistor and is grounded. The low-dropout
linear regulator circuit with the high
power supply rejection ratio improves the
power supply rejection ratio.