Low-dropout linear regulator circuit with high power supply rejection ratio

A high power supply rejection ratio, low dropout linear technology, applied in instruments, regulating electrical variables, control/regulating systems, etc., can solve the problems of low power supply rejection, difficult to achieve power supply rejection ratio, and difficult to meet the requirements of on-chip system indicators. Wide application range and good power supply rejection ratio

Inactive Publication Date: 2019-04-26
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the load capacitance of the low dropout linear regulator becomes smaller and the load current is larger and larger, it is difficult for the power supply rejection ratio to reach the required index, thus affecting the overall performance of the entire low dropout linear regulator
[0003] The power supply rejection ratio of the traditional low-dropout linear regulator is relatively low, and it is difficult to meet the power supply rejection ratio index requirements of the power supply system for the low-dropout linear regulator. In addition, the on-chip low-dropout linear regulator has become a low-dropout linear regulator. The development direction of the compressor makes it more difficult to meet the system-on-chip requirements

Method used

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  • Low-dropout linear regulator circuit with high power supply rejection ratio
  • Low-dropout linear regulator circuit with high power supply rejection ratio
  • Low-dropout linear regulator circuit with high power supply rejection ratio

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Embodiment Construction

[0043] The technical solutions of the present invention will be further described through specific embodiments below in conjunction with the accompanying drawings.

[0044] like figure 1 Shown is a topological structure diagram of a high power supply rejection ratio low dropout linear regulator circuit proposed by the present invention, including a negative feedback loop composed of a bias module, an error amplifier, a buffer and an output stage. The output stage consists of power transistors and feedback resistors, such as figure 1 and figure 2 As shown, the feedback resistor includes the first resistor R1 and the second resistor R2. The first resistor R1 and the second resistor R2 are the same type of resistors. The value of the feedback resistor should fully consider the current required by the load; the power tube width-to-length ratio It must be large enough to ensure sufficient current extraction. The power tube can be a PMOS tube or an NMOS tube. Taking the power tub...

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Abstract

The invention provides a low-dropout linear regulator circuit with a high power supply rejection ratio, and belongs to the field of analog circuit integration. The low-dropout linear regulator circuitcomprises a bias module, an error amplifier, a buffer and an output stage, wherein the bias module provides bias voltage; a positive input end of the error amplifier is connected to reference voltage, a negative input end of the error amplifier is connected to feedback voltage, and an output end of the error amplifier passes through the buffer and the output stage to be connected to an output endof an LDO; the buffer comprises an amplification stage, a high-pass filter and a current source, and the amplification stage is connected between an input end and output end of the buffer; the current source is connected between power supply voltage and the output end of the buffer; the high-pass filter comprises a first NMOS transistor, a first PMOS transistor, a second PMOS transistor and a first capacitor, a grid electrode of the first PMOS transistor is connected with the bias voltage, a source electrode of the first PMOS transistor is connected with power supply voltage and is connectedto a drain electrode of the first PMOS transistor, a grid electrode of the second PMOS transistor and a grid electrode and drain electrode of the first NMOS transistor after passing through the firstcapacitor; a source electrode of the second PMOS transistor is connected with the output end of the buffer, and a drain electrode of the second PMOS transistor is connected with a source electrode ofthe first NMOS transistor and is grounded. The low-dropout linear regulator circuit with the high power supply rejection ratio improves the power supply rejection ratio.

Description

technical field [0001] The invention belongs to the field of analog circuit integration, in particular to a low-dropout linear regulator (LDO) circuit. Background technique [0002] In today's society, with the continuous advancement of technology, electronic products have become a must for everyone. The power management chip of the electronic system has a very important impact on the whole machine. The low dropout linear regulator is an important solution for the system on chip. . As the load capacitance of the low dropout linear regulator becomes smaller and the load current is larger and larger, it is difficult for the power supply rejection ratio to meet the required index, thereby affecting the overall performance of the entire low dropout linear regulator. [0003] The power supply rejection ratio of the traditional low-dropout linear regulator is relatively low, and it is difficult to meet the power supply rejection ratio index requirements of the power supply system...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/575
CPCG05F1/575
Inventor 李靖王鑫森王翊舟
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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