71results about "Amplifiers using switched capacitors" patented technology

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

A harmonic modeling method of a power amplifier solves the problem that a traditional modeling method is not suitable for harmonic modeling analysis of a high-switching-frequency topological structure, and comprises the following steps: obtaining baseband harmonic and sideband harmonic caused by modulation nonlinearity according to the number of parallel half bridges, a modulation wave function and a carrier function in the power amplifier; according to the topological structure of the power amplifier, obtaining a circuit equation of the topological structure in the dead-zone time period; calculating the current amplitude envelope of the resonant inductor; and calculating a voltage error caused by the dead-zone time period according to the calculated current amplitude envelope in combination with a circuit equation of the dead-zone time period, performing Fourier decomposition on the voltage error to obtain distortion harmonics caused by the dead-zone time period of the power amplifier, and obtaining total harmonics in combination with the obtained baseband harmonics and sideband harmonics. According to the invention, the switching frequency when the total harmonic distortion is the lowest can be obtained through modeling.

The invention provides a multimode radio frequency power amplifier module, a radio frequency chip and a mobile terminal. The module comprises two power amplifiers, four switching circuits and a control circuit, an input GSM low-frequency-band radio-frequency signal and a low-frequency-band radio-frequency signal of other communication systems are input into the low-frequency-band power amplifier through the first input switch circuit, and the output of the low-frequency-band power amplifier is connected with one of the low-frequency-band radio-frequency output ports through the first output switch circuit. An input GSM high-frequency-band radio frequency signal and a medium-frequency-band radio frequency signal of other communication systems are input into the medium-frequency-band power amplifier through a second input switch circuit, and the output of the medium-frequency-band power amplifier is connected with one of the medium-frequency-band radio frequency output ports through a second output switch circuit; and the control circuit provides proper working voltage for the low-frequency-band power amplifier and the middle-frequency-band power amplifier respectively. The integration level of the radio frequency amplifier module is improved, the area is reduced, and the cost of the mobile terminal is reduced.

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.

The invention discloses a three-level inverter circuit, a gradient amplifier and electronic equipment. The three-level inverter circuit comprises four bridge arm switches, two clamping switches, an absorption capacitor and an inductor. The joint of the first switch and the second switch is connected with one end of the absorption capacitor and the first clamping switch, the joint of the third switch and the fourth switch is connected with the other end of the absorption capacitor and the second clamping switch, and the joint of the first clamping switch and the second clamping switch is connected with a neutral point. The joint of the second switch and the third switch is connected with one end of the inductor, the other end of the inductor is connected with a power grid end, and in the zero-crossing switching process of the three-level inverter circuit, after one of the second switch and the third switch is controlled to be switched off, the other one of the second switch and the third switch is controlled to be switched on. According to the three-level inverter circuit, the energy of the absorption capacitor can be fed back to the inductor in the zero-crossing switching process, so that the loss is reduced.

A touch display device and a weighted touch sensing method of a touch controller for providing an accurate touch sensing performance and a high quality of image display are disclosed. The touch display device may include a display panel in which a plurality of subpixels are disposed and a plurality of touch electrodes overlapping one or more of the plurality of subpixels are disposed, and a touch driving circuit configured to supply a touch driving signal including a plurality of pulses to one or more of the plurality of touch electrodes, the touch driving circuit configured to output respective touch driving signals having different numbers of pulses in a first sensing sub-period and a second sensing sub-period in the period of one frame.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs. Within each adjacent pair, one column includes a cell storing a W+ value, and another column includes a cell storing a W- value. The adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system includes a first array of non-volatile memory cells storing W+ values ​​and a second array of non-volatile memory cells storing W- values.

Devices, systems, and methods providing for improved detection of a high frequency component in an input signal are described. A detector includes a detector stage configured to receive an input signal and generate a detection signal that represents the input signal. The detector also includes an amplifier stage that configured to receive the detection signal from the detector stage and amplify the detection signal to generate an output signal that indicates whether the input signal includes a high frequency component. In some examples, the detector stage includes a switched cap detector and the amplifier stage includes a first switched cap amplifier and a second switched cap amplifier. In some examples, the switched cap detector and the first switched cap amplifier are operated responsive to a first clock signal, and the second switched cap amplifier is operated responsive to a second clock signal different than the first clock signal.

The application provides an amplification circuit, wherein the amplification circuit comprises an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone elimination circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between the input terminal and the output terminal of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit comprises an energy storage module, and the energy storage module comprises a switched capacitor. The aliasing tone elimination circuit is coupled between the input terminal of the amplification circuit and the input terminal of the amplifier, and is configured to generate a signal according to the input signal to eliminate or reduce aliasing tones of the feedback signal.

The invention relates to an open-loop modulation transmitter with a harmonic suppression switched capacitor power amplifier. The transmitter comprises a sixteen-phase delay locked loop, a binary frequency shift keying modulator and the harmonic suppression switched capacitor power amplifier. The sixteen-phase delay locked loop provides sixteen paths of clock signals with equal phase difference to the binary frequency shift keying modulator, and the sixteen paths of clock signals are used as input signals of the binary frequency shift keying modulator; the binary frequency shift keying modulator is connected with the harmonic suppression switched capacitor power amplifier and provides a modulation signal for the harmonic suppression switched capacitor power amplifier; and the harmonic suppression switched capacitor power amplifier is used for amplifying the modulation signal and suppressing a harmonic component so as to output the modulation signal after harmonic suppression. According to the invention, high data rate transmission can be supported, the higher harmonic suppression capability is provided, the design requirement of a matching network can be relaxed while the frequency spectrum purity is ensured, the chip area is reduced, and the system cost is reduced.

The invention discloses a differential hybrid supply generator and supply modulator with multi-output regulation. In some embodiments, a hybrid generator / modulator includes a regulation stage having a single input and at least two outputs, the regulation stage configured to receive an input voltage at the single input and to provide two intermediate voltages at respective ones of the at least two outputs; and a multilevel converter configured to receive the two intermediate voltages and provide an output voltage having a voltage level corresponding to a voltage level of one of the two intermediate voltages or at least one other voltage level synthesized from the two intermediate voltages.

An adding circuit for multi-channel signals and an implementation method thereof are disclosed. The adding circuit for multi-channel signals includes an operational amplifier, a plurality of charge and discharge circuits, a charge transfer circuit, a switch sequence and a control circuit. In this disclosure, the duty cycle of each charge and discharge circuit and the charge transfer circuit can be programmed and preset according to the actual needs, which is not only suitable for the static voltage adding circuit, but also suitable for the dynamic voltage adding circuit. When there are multi-channel signals, the output interference caused by individual signals can be prevented. The area of the adding circuit can be greatly reduced. The adding circuit can be IP-based, controlled by programing and presetting a variety of combined adding algorithms, so the chip cost can be saved and a wide applicability in detection and monitoring can be provided.

Described are techniques for analog clipping for a switched capacitor power amplifier comprising an array of a plurality of unit cells shareable between in-phase (I) and quadrature-phase (Q) signal components. A pair of control bits is associated with each unit cell, comprising a first control bit to selectively enabling the unit cell to use the I component, and a second control bit to selectively enabling the unit cell to use the Q component. A truth table is configured for a first subset and a second subset of unit cells, and causes the unit cells of the first subset to be driven by the I component in response to a double-enabled condition of the respective pair of control bits. The truth table is configured to cause the unit cells of the second subset to be driven by the Q component in response to the double-enabled condition.

The present disclosure relates to a charge amplifier circuit (10) for a capacitive sensing arrangement (80), the charge amplifier circuit (10) comprising: - an first amplifier stage (20) comprising a first amplifier input (22), a second amplifier input (23) connectable to the capacitive sensing arrangement (80), and comprising a first amplifier output (24) and a second amplifier output (25), - a second amplifier stage (30) comprising a first amplifier input (32), a second amplifier input (33), a first amplifier output (34) and a second amplifier output (35), and - a switched capacitor arrangement (40) between the first amplifier stage (20) and the second amplifier stage (30), the switched capacitor arrangement (40) comprising a first integration capacitor (42), a second integration capacitor (43), a number of first switches (66, 67) and a number of second switches (68, 69).

A charge amplifier circuit (10) for a capacitive sensing arrangement (80), the charge amplifier circuit (10) including: an first amplifier stage (20) including a first amplifier input (22), a second amplifier input (23) connectable to the capacitive sensing arrangement (80), and including a first amplifier output (24) and a second amplifier output (25), a second amplifier stage (30) including a first amplifier input (32), a second amplifier input (33), a first amplifier output (34) and a second amplifier output (35), and a switched capacitor arrangement (40) between the first amplifier stage (20) and the second amplifier stage (30), the switched capacitor arrangement (40) including a first integration capacitor (42), a second integration capacitor (43), a number of first switches (66, 67) and a number of second switches (68, 69).

In some embodiments, a hybrid generator / modulator comprises: a regulation stage having a single input and at least two outputs, the regulation stage configured to receive an input voltage at the single input and to provide two intermediate voltages at respective ones of the at least two outputs; and a multilevel converter configured to receive the two intermediate voltages and provide an output voltage having a voltage level corresponding to a voltage level of one of the two intermediate voltages or at least one other voltage level synthesized from the two intermediate voltages.

Disclosed are a high-linearity low-noise amplifier, a chip, and an electronic device. The low-noise amplifier comprises a primary-stage amplification unit, at least one secondary-stage amplification unit, a drive unit, a configurable load unit, an input impedance matching unit and an output impedance matching unit, and further comprises a switched capacitor branch; wherein the input end of the at least one secondary-stage amplification unit is connected via the switched capacitor branch to the input end of the primary-stage amplification unit, and the input end of the secondary-stage amplification unit is provided with an independent bias voltage; in a low-gain operating mode, the switched capacitor branch is closed, and at the same time, a secondary amplification unit path connected to the switched capacitor branch is opened.

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

The present invention provides an amplifier circuit, wherein the amplifier circuit includes an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone cancellation circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between an input node and an output node of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit includes a storage block including a switched-capacitor. The aliasing tone cancellation circuit is coupled between the input terminal of the amplifier circuit and the input node of the amplifier, and configured to generate a signal to cancel or reduce an aliasing tone of the feedback signal according to the input signal.

A tracker circuit (1) includes a pre-regulator circuit (10) configured to convert an input voltage into a regulated voltage using a power inductor (L71), a switched-capacitor circuit (20) configured to generate a plurality of discrete voltages, based on the regulated voltage, and a power modulation circuit (30) configured to select at least one voltage from the plurality of discrete voltages and output the at least one voltage to an output terminal (141), the pre-regulator circuit (10) is configured to output the input voltage or the regulated voltage to an output terminal (142) via a bypass path (BP1) configured to bypass the switched-capacitor circuit (20) and the power modulation circuit (30), and the bypass path (BP1) is configured to connect, to the output terminal (142), a path (P1) between the power inductor (L71) and the switched-capacitor circuit (20).

To provide an analog neural memory array in which synapsis weights are stored in differential cell pairs in an array; power consumption is substantially constant from a bit line to a bit line within the array when cells are being read; and weight mapping is performed adaptively for optimal performance in power and noise.SOLUTION: An analog neural memory system comprises an array of non-volatile memory cells which can be used in a vector by matrix multiplication (VMM) array, the cells arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, within each adjacent pair, one column in the adjacent pair comprising cells storing W+ values, and one column in the adjacent pair comprising cells storing W- values. The adjacent cells in the adjacent pair store a differential weight W, according to the formula W=(W+)-(W-). In another embodiment, a system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W- values.SELECTED DRAWING: Figure 21A

The invention discloses a switch matrix with automatic gain control (AGC), a radio frequency module and a radio frequency signal control method, an automatic gain control circuit in the switch matrix comprises a first control circuit and a second control circuit, the first control circuit comprises a first numerical control attenuator, and an input signal of the automatic gain control circuit is input into the first numerical control attenuator; an output signal of the first numerical control attenuator is configured as an output signal of the automatic gain control circuit; the second circuit comprises a first power divider, a first output end of the first power divider is electrically connected with a first detector and the FPGA in sequence, a second output end of the first power divider is electrically connected with a first amplifier, a second detector and the FPGA in sequence, and an input signal of the automatic gain control circuit is input into the first power divider, is divided into two paths of signals by the first power divider and then is input into the FPGA; the output end of the FPGA is electrically connected with the input end of the first numerical control attenuator. According to the invention, a large dynamic adjustment range can be maintained, and the signal processing precision can be improved.

The invention provides a switching type capacitor power amplification device and a method for controlling the same. A switched capacitor power amplification device includes an array of a plurality of unit cells that can be shared between an in-phase-I component and a quadrature-phase-Q component. A pair of control bits is associated to each unit cell, including a first control bit for selectively activating the unit cell to use an in-phase component, and a second control bit for selectively activating the unit cell to use a quadrature phase component. The truth table is configured to a first subset and a second subset of the plurality of unit cells, such that the first subset of unit cells is driven by in-phase components in response to a dual start condition of control bits for individual pairs. The truth table is configured such that the second subset of unit cells is driven by the quadrature phase component in response to the dual start condition.

A power amplifier comprises a main switching capacitor power amplifier (main SCPA) and a peak SCPA connected in parallel to the main SCPA. The main SCPA comprises a plurality of first cells electrically coupled in parallel. Each first cell comprises a first inverter, a second three-state inverter connected in parallel to the first inverter, and a first capacitor connected in series with both the first and second inverters. Each first cell also comprises first control logic for applying a local oscillator (LO) signal to the first inverter or for setting the first inverter to a static logic state in response to a first control signal, and for applying the LO signal to the second inverter or for setting the second inverter to a high-impedance state in response to a second control signal.

The invention provides a ripple elimination circuit with a self-zeroing function and a chopping operational amplifier, and relates to the technical field of analog integrated circuits, and the ripple elimination circuit comprises an input sampling unit, a post-stage chopping unit, an integral self-zeroing unit and a feedback unit. A first switch group is arranged in the input sampling unit, and a corresponding zero-setting switch group is arranged in the integral self-zero-setting unit. Through specific clock control, when the integral self-zeroing unit is in an offset voltage sampling phase, the first switch group is turned off, and an input sampling capacitor is physically isolated from a subsequent integral zeroing loop; and in a signal amplification phase, the first switch group is switched on, and a signal path is established. According to the design, the interference of external ripples on the offset voltage storage process at the sampling phase is effectively blocked, and the accuracy of the compensation current is remarkably improved in combination with optimized sequential control, so that an excellent ripple elimination effect and extremely low residual offset voltage are realized, and the method is suitable for an ultra-high-precision analog operational amplifier.

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Described are techniques for analog clipping for a switched capacitor power amplifier comprising an array of a plurality of unit cells shareable between in-phase (I) and quadrature-phase (Q) signal components. A pair of control bits is associated with each unit cell, comprising a first control bit to selectively enabling the unit cell to use the I component, and a second control bit to selectively enabling the unit cell to use the Q component. A truth table is configured for a first subset and a second subset of unit cells, and causes the unit cells of the first subset to be driven by the I component in response to a double-enabled condition of the respective pair of control bits. The truth table is configured to cause the unit cells of the second subset to be driven by the Q component in response to the double-enabled condition.

The embodiment of the invention provides a zero-voltage switch control device, an audio amplifier and a chip. The voltage switch control device comprises a voltage detection module and a zero-voltage switch control module, the voltage detection module is used for detecting the change of the output voltage of a positive power unit and the change of the input voltage of a negative power unit included in the power stage, and the zero voltage switch control module is used for delaying a driving signal according to the change of the output voltage of the positive power unit and the change of the input voltage of the negative power unit. According to the invention, the zero-voltage switch control device delays the driving signal according to the change of the output voltage of the positive power unit and the input voltage of the negative power unit included in the power level, so that the signal distortion problem caused by additional delay can be avoided while zero-voltage starting of part of power tubes in the power level is realized; and the working frequency and the duty ratio of the power level are not changed in the process of performing zero-voltage starting so as to reduce the switching loss.