157results about "Amplifiers using switched capacitors" patented technology

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

A multiplying digital-to-analog converter (MDAC) has two input terminals and two output terminals and includes: an analog-to-digital converter (ADC), a selection circuit, first and second sampling and amplifying circuits, an operational amplifier, and an amplification and level shifting circuit. The ADC generates a selection signal according to first and second input signals. The selection circuit selects two reference voltages from a plurality of preset voltages according to the selection signal. The first sampling and amplifying circuit samples and amplifies the first input signal according to one of the two reference voltages. The second sampling and amplifying circuit samples and amplifies the second input signal according to the other reference voltage. The operational amplifier has first and second output nodes. The amplification and level shifting circuit amplifies the first and second input signals and level shifts voltages at the first and second output nodes.

The present disclosure relates to an amplifier circuit comprising a main amplifier circuit comprising a plurality of first switched-capacitor, SC, house-of-cards, HoC, amplifier cells coupled in parallel between an input and an output of the main amplifier circuit, at least one peak amplifier circuit comprising a plurality of second SC HoC amplifier cells coupled in parallel between an input and an output of the peak amplifier circuit, wherein the output of the main amplifier circuit and the output of the peak amplifier circuit are coupled to a common load.

A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.

In an exemplary aspect, a tracker circuit is provided that includes a first switch circuit configured to generate a plurality of discrete voltages, based on an input voltage, a second switch circuit configured to select at least a first voltage from the plurality of discrete voltages as a supply voltage, a filter circuit that is connected to the second switch circuit and is configured to filter the supply voltage and generate a filtered supply voltage that is provided to an amplifier via a voltage supply path between the filter circuit and the amplifier, and a third switch circuit including a capacitor and a switch that are connected in series between a ground and the voltage supply path.

Power amplifiers with supply capacitor switching are provided herein. In certain embodiments, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal, a power management circuit that controls a voltage level of a supply voltage of the power amplifier, a supply capacitor having a first end connected to the supply voltage, and a bulk n-type field-effect transistor (NFET) switch. The power management circuit is operable in multiple supply control modes (for example, an average power tracking mode and an envelope tracking mode). Additionally, the bulk NFET switch is controlled based on the supply control mode of the power management circuit. The bulk NFET switch includes a ground NFET in series with a second end of the supply capacitor and a ground voltage, and a discharge NFET connected between the second end of the supply capacitor and the supply voltage.

A tracker circuit includes a pre-regulator circuit configured to convert an input voltage into a regulated voltage using a power inductor, a switched-capacitor circuit configured to generate a plurality of discrete voltages, based on the regulated voltage, and a power modulation circuit configured to select at least one voltage from the plurality of discrete voltages and output the at least one voltage to a first output terminal. Further, the tracker circuit includes one or more bypass paths configured to bypass at least the switched-capacitor circuit and the power modulation circuit, and to provide a second supply voltage from the pre-regulator circuit to a second output terminal, the second supply voltage is output by the second output terminal.

A tracker module is provided that includes a module laminate, and an integrated circuit disposed at the module laminate. The integrated circuit includes at least one switch included in a pre-regulator circuit; at least one switch included in a switched-capacitor circuit; at least one switch included in an output switching circuit; and a digital control circuit. In plan view of the module laminate, at least one of the at least one switch included in the output switching circuit; or the digital control circuit is disposed between the at least one switch included in the pre-regulator circuit and the at least one switch included in the switched-capacitor circuit.

A harmonic modeling method of a power amplifier solves the problem that a traditional modeling method is not suitable for harmonic modeling analysis of a high-switching-frequency topological structure, and comprises the following steps: obtaining baseband harmonic and sideband harmonic caused by modulation nonlinearity according to the number of parallel half bridges, a modulation wave function and a carrier function in the power amplifier; according to the topological structure of the power amplifier, obtaining a circuit equation of the topological structure in the dead-zone time period; calculating the current amplitude envelope of the resonant inductor; and calculating a voltage error caused by the dead-zone time period according to the calculated current amplitude envelope in combination with a circuit equation of the dead-zone time period, performing Fourier decomposition on the voltage error to obtain distortion harmonics caused by the dead-zone time period of the power amplifier, and obtaining total harmonics in combination with the obtained baseband harmonics and sideband harmonics. According to the invention, the switching frequency when the total harmonic distortion is the lowest can be obtained through modeling.

The invention provides a multimode radio frequency power amplifier module, a radio frequency chip and a mobile terminal. The module comprises two power amplifiers, four switching circuits and a control circuit, an input GSM low-frequency-band radio-frequency signal and a low-frequency-band radio-frequency signal of other communication systems are input into the low-frequency-band power amplifier through the first input switch circuit, and the output of the low-frequency-band power amplifier is connected with one of the low-frequency-band radio-frequency output ports through the first output switch circuit. An input GSM high-frequency-band radio frequency signal and a medium-frequency-band radio frequency signal of other communication systems are input into the medium-frequency-band power amplifier through a second input switch circuit, and the output of the medium-frequency-band power amplifier is connected with one of the medium-frequency-band radio frequency output ports through a second output switch circuit; and the control circuit provides proper working voltage for the low-frequency-band power amplifier and the middle-frequency-band power amplifier respectively. The integration level of the radio frequency amplifier module is improved, the area is reduced, and the cost of the mobile terminal is reduced.

A tracker circuit is provided that includes a switched-capacitor circuit configured to generate a plurality of discrete voltages based on a first input voltage; a supply modulator configured to selectively output at least one of the plurality of discrete voltages to a power amplifier; a bypass path configured to bypass the switched-capacitor circuit and the supply modulator to output the first input voltage to the power amplifier; and a switch configured to switch between a connection and a disconnection of the bypass path.

The invention discloses a switched capacitor circuit, a signal receiving chip and an Ethernet transceiver. The switched capacitor circuit comprises a first group of capacitors, a second group of capacitors, a third group of capacitors, a fully differential operational amplifier and a switch assembly. According to the technical scheme, on one hand, the switched capacitor circuit is controlled under the external clock signal to achieve the alternating process of the sampling phase state and the amplification phase state, a negative feedback loop is formed in the amplification phase state, and the frequency response and amplitude balance of the signal are ensured through the negative feedback loop. And on the other hand, compared with a traditional linear equalizer, the transfer function of the switched capacitor circuit in the technical scheme is only related to the capacitance ratio theoretically and is not easily influenced by process deviation, power supply voltage or temperature change, so that stable equalization frequency range and equalization strength are achieved, the stability of equalization capability is ensured, and the service life of the equalizer is prolonged. And the method is applied to an Ethernet receiving channel to omit CTLE, so that the structural design can be simplified.

A circuit may include a two-stage feedforward compensated operational transconductance integrated amplifier, and the two-stage feedforward compensated operational transconductance integrated amplifier may include an input terminal, an output terminal, a signal path between the input terminal and the output terminal, the signal path comprising a first signal path gain stage and a second signal path gain stage, and ripple rejection circuitry coupled between the input terminal and an intermediate node of the signal path located between the first signal path gain stage and the second signal path gain stage. The ripple rejection circuitry may include a first ripple rejection circuitry gain stage coupled at its input to the input terminal and coupled at its output to an input terminal of a chopper circuit, a notch filter coupled at its input to an output terminal of the chopper circuit, and a second ripple rejection circuitry gain stage coupled at its input to an output terminal of the notch filter and coupled at its output to the intermediate node.

The present invention relates to the technical field of analog circuits. Disclosed are a low-voltage floating inverter amplifier and a switched-capacitor analog-to-digital converter. The low-voltage floating inverter amplifier comprises a first self-biased inverter, a second self-biased inverter, and an energy storage capacitor connected in parallel. Both the first self-biased inverter and the second self-biased inverter are clock-controlled inverters that self-generate bias voltages. One end of the parallel connection is connected to a power supply voltage by means of a reset switch, and the other end of the parallel connection is connected to a ground voltage by means of a reset switch. Each of an input end of the first self-biased inverter and an input end of the second self-biased inverter is connected to an input signal, and is connected to a ground voltage by means of a reset switch. Each of an output end of the first self-biased inverter and an output end of the second self-biased inverter is provided with an amplification switch. The reset switches and the amplification switches are closed in an alternating manner by means of clock control. The low-voltage floating inverter amplifier is compatible with power supplies below 1 V under low-cost conditions, reducing power consumption and enhancing energy efficiency.

An amplifying device includes a main amplifier; a first feedback circuit coupled between an input terminal of the main amplifier and an output terminal of the main amplifier; an input coupling circuit coupled between the input terminal of the main amplifier and a first node; and an amplifying feedback circuit coupled between the output terminal of the main amplifier and the first node, wherein the first feedback circuit and the amplifying feedback circuit are negative feedback circuits.

A high voltage driver is provided that includes a PMOS stack of transistors arranged in series between a power supply node and an output node. The high voltage driver also includes an NMOS stack of transistors arranged between the output node and ground.

An apparatus includes a plurality of gain stages connected in parallel between a first bias voltage and ground, where each gain stage includes an amplification portion and a current control portion including a first selectable signal path connected between an output of the amplification portion and a signal output, and a second selectable signal path connected between an output of the amplification portion and a signal output. And a second selectable signal path connected between the output of the amplification section and ground by a shunt device.

In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.

The invention discloses a three-level inverter circuit, a gradient amplifier and electronic equipment. The three-level inverter circuit comprises four bridge arm switches, two clamping switches, an absorption capacitor and an inductor. The joint of the first switch and the second switch is connected with one end of the absorption capacitor and the first clamping switch, the joint of the third switch and the fourth switch is connected with the other end of the absorption capacitor and the second clamping switch, and the joint of the first clamping switch and the second clamping switch is connected with a neutral point. The joint of the second switch and the third switch is connected with one end of the inductor, the other end of the inductor is connected with a power grid end, and in the zero-crossing switching process of the three-level inverter circuit, after one of the second switch and the third switch is controlled to be switched off, the other one of the second switch and the third switch is controlled to be switched on. According to the three-level inverter circuit, the energy of the absorption capacitor can be fed back to the inductor in the zero-crossing switching process, so that the loss is reduced.

A touch display device and a weighted touch sensing method of a touch controller for providing an accurate touch sensing performance and a high quality of image display are disclosed. The touch display device may include a display panel in which a plurality of subpixels are disposed and a plurality of touch electrodes overlapping one or more of the plurality of subpixels are disposed, and a touch driving circuit configured to supply a touch driving signal including a plurality of pulses to one or more of the plurality of touch electrodes, the touch driving circuit configured to output respective touch driving signals having different numbers of pulses in a first sensing sub-period and a second sensing sub-period in the period of one frame.

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs. Within each adjacent pair, one column includes a cell storing a W+ value, and another column includes a cell storing a W- value. The adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system includes a first array of non-volatile memory cells storing W+ values ​​and a second array of non-volatile memory cells storing W- values.

A tracker module (100A) includes a module laminate (90) and one or more integrated circuits that are arranged on the module laminate (90) and that includes an integrated circuit (80). The integrated circuit (80) includes a switch included in a pre-regulator circuit (10), at least one switch included in a switched-capacitor circuit (20), a first IC terminal connected to the switch included in the pre-regulator circuit (10), and a second IC terminal connected to one of the at least one switch included in the switched-capacitor circuit (20). The at least one integrated circuit includes a switch included in a supply modulator (30). The module laminate (90) includes a signal line (901) with which the first IC terminal is connected to the second IC terminal.

The present invention provides a dynamic comparator and a circuit system using the same, which includes a differential stage, a switching unit, and a switched charge storage unit. The switched charge storage unit includes a plurality of switching transistors and a charge storage capacitor electrically connected to the plurality of switching transistors. When the dynamic comparator switches from a comparison state to a reset state, the voltage at the first end or the second end of the charge storage capacitor rises from half of the system voltage to the system voltage, so as to achieve charge recycling. Thus, the present invention can enable the dynamic comparator to have lower power consumption and lower charging and discharging currents.

The present invention is in the field of booster stage circuit for a power amplifier, and an external supply voltage power amplifier comprising said booster stage circuit, such as for amplifying an electronic signal to a speaker system. These amplifiers may be provided with an external supply voltage.

A tracker module (1A) is provided with a module substrate (90), and an integrated circuit (80) disposed on the module substrate (90), the integrated circuit (80) having at least one switch included in a preregulator circuit (10), at least one switch included in a switched capacitor circuit (20), at least one switch included in an output switching circuit (30), and a digital control circuit (60), and the digital control circuit (60) is configured so that, in a plan view of the module substrate (90), the digital control circuit (60) is configured so that the digital control circuit (60) is switched between the preregulator circuit (10) and the switched capacitor circuit (20). At least one of the at least one switch included in the output switching circuit (30) and the digital control circuit (60) is disposed between the at least one switch included in the preregulator circuit (10) and the at least one switch included in the switched capacitor circuit (20).

Devices, systems, and methods providing for improved detection of a high frequency component in an input signal are described. A detector includes a detector stage configured to receive an input signal and generate a detection signal that represents the input signal. The detector also includes an amplifier stage that configured to receive the detection signal from the detector stage and amplify the detection signal to generate an output signal that indicates whether the input signal includes a high frequency component. In some examples, the detector stage includes a switched cap detector and the amplifier stage includes a first switched cap amplifier and a second switched cap amplifier. In some examples, the switched cap detector and the first switched cap amplifier are operated responsive to a first clock signal, and the second switched cap amplifier is operated responsive to a second clock signal different than the first clock signal.

An apparatus includes a multi-stage amplifier and a feedback switch. The multistage amplifier includes a first amplifier having a first input, a second input, and an output, a second amplifier having an input and an output, wherein the input of the second amplifier is coupled to the output of the first amplifier, and a third amplifier having an input and an output, wherein the input of the third amplifier is coupled to the output of the first amplifier. The feedback switch is coupled between the output of the third amplifier and the second input of the first amplifier.

The application provides an amplification circuit, wherein the amplification circuit comprises an input terminal, a capacitor, an amplifier, a feedback circuit and an aliasing tone elimination circuit. The input terminal is configured to receive a first input signal. The capacitor is coupled to the input terminal. The amplifier is configured to receive the input signal through the capacitor to generate an output signal. The feedback circuit is coupled between the input terminal and the output terminal of the amplifier, and is configured to generate a feedback signal according to the output signal, wherein the feedback circuit comprises an energy storage module, and the energy storage module comprises a switched capacitor. The aliasing tone elimination circuit is coupled between the input terminal of the amplification circuit and the input terminal of the amplifier, and is configured to generate a signal according to the input signal to eliminate or reduce aliasing tones of the feedback signal.

The integrator circuit includes an operational amplifier, a first capacitor coupled to an input of the operational amplifier, a second capacitor, and a second switch configured to electrically couple a first terminal of the second capacitor to a second terminal of the first capacitor coupled in parallel with the first capacitor such that a first terminal of the first capacitor is configured to be electrically coupled to a first terminal of the second capacitor by the first switch.