263results about "Signal/carrier strength dependant limiting amplitude" patented technology

The present invention is a hybrid RF-digital signal processor-based filter for multiband radio architectures systems capable of spectrum re-farming and software defined radios. It performs low-loss frequency agile multiple notch filtering at RF where a large dynamic range exists at a filter input between signals in a stopband and passband. It is a frequency dependent signal attenuation apparatus having two paths connected together by directional couplers. The first path comprising a component such as a delay component or duplexer. The second path comprising a bandstop filter connected to a down converter, a digital filter, and an up converter. At the output of a power amplifier, the invention can be used to attenuate spurs, or noise within bands with strict emission constraints. At the input of a low noise amplifier, the invention can be used to attenuate blockers and transmitter noise outside of the receiver passband.

An automatic tuning system for a magnetic field generating tuned circuit includes a processor configured to maintain the resonant frequency of a tuned circuit equal to a reference frequency. The tuned circuit is driven by a power amplifier whose output provides an amplified signal at the reference frequency. The tuned circuit includes a magnetic field generating inductor and a bank of individually switchable capacitors controlled by the processor capable of adding and removing the respective capacitances to and from the tuned circuit. The inductor includes a Faraday shield to shield the tuned circuit from the influence of electric fields. In an embodiment of the invention, the variable capacitor is in the form of a diode variable capacitor (varicap) in parallel circuit relationship with the tuned circuit capacitor and the inductor. In an alternate embodiment the inductor and a fixed capacitor are in series circuit relationship with the varicap in parallel circuit relationship with the fixed capacitor and the tuning sequence relies on a phase locked loop using the phase of a reference frequency signal and the phase of the inductor voltage as control parameters.

A tunable filter has a plurality of variable capacitors and a plurality of inductor elements, each being formed on a common substrate, a filter circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a monitor circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a detecting circuit which detects a prescribed circuit constant of the monitor circuit, a storage which stores information relating to a reference circuit constant of the monitor circuit, and a capacitance control circuit which controls capacitance of the variable capacitors in the monitor circuit and capacitance of the variable capacitors in the filter circuit, based on a result detected by the detecting circuit and information stored in the storage.

An apparatus and method for filtering a signal in a phase lock loop is disclosed. An typical apparatus for filtering a phase error signal comprises a first filter subcircuit receiving a phase error signal from a phase comparator and filtering the error signal when enabled, a second filter subcircuit receiving the phase error signal from the phase comparator and filtering the error signal when enabled and first and second enable switches which are activated in combination to control filtering of at the error signal. The first filter subcircuit is enabled by activating a first combination of the enable switches and the second filter subcircuit is enabled by activating a second combination of the enable switches. A fast acquisition subcircuit can also be used to temporarily underdampen the filter and improve overall performance of the phase lock loop circuit. The filter can be used to obtain multimode operation in a cellular radio.

The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format. The control signal (CP) influences a magnitude of at least one component value in the adjustable phase shift between the periodic reference signal (R) and the periodic phase shifted signal (R*) attains a calibrated value being as close as possible to a desired value. A latch (210) forwards at least one signal element of the control signal (CP) for setting of at least one component value in the analogue filter (201) in accordance with a setting of at least one component value in the adjustable phase shifter (203) which produces the calibrated value.

A PAM-N decision feedback equalizer (DFE) comprises a coefficient computation unit; a feedback unit that mitigates, using computed feedback coefficients, effects of interference from data symbols; an error-and-decision unit for at least computing a least error value respective to one of a plurality of decision levels, wherein the least error value indicates a difference of a pseudo equalized input PAM-N data symbol from an optimal position of the one of the plurality of decision levels, wherein the one of the plurality of decision levels corresponds to a modulation level used to modulate data in the input PAM-N data symbol; and a calibration unit for adaptively setting the plurality of decision levels based, in part, on the least error value, thereby enabling for compensating for gain changes resulted by a cable on which the input PAM-N data symbol is received and further compensating for embedded offsets of the error-and-decision unit.

Methods, systems and apparatus for filter design, analysis and adjustment are provided. Various embodiments may include, for example, methods, systems and apparatus for electric signal filter tuning. Embodiments may also include design techniques for planar electric signal (e.g., RF signals) filter tuning. In at least an embodiment of the present invention a technique for filter tuning is provided which may include parameter extraction, optimization and tuning recipes techniques that may require only a single permanent filter tuning. In at least another embodiment a system and method of filter design, analysis and adjustment according to the present invention includes use of tuning that may be set using a mechanical scribing tool or a laser trimming device. In at least one other embodiment, a filter tuning technique may be provided and include providing trimming tabs on a resonator edge that may be disconnected or trimmed for filter tuning.