Systems and methods for phase detection are disclosed. A collapsible three-stage pipeline includes a first register in a first stage having a first
clock signal having first
clock edges, a second register in a second stage that receives a first
signal from the first stage, and having a second
clock signal having second clock edges, and a third register in a third stage that receives a second signal from the second stage, and having a third
clock signal having third clock edges, wherein each second clock edge has a corresponding first clock edge and a corresponding third clock edge. The circuitry may further include a two-stage pipeline including fourth and fifth stages, a counter that provides an input signal into the collapsible three-stage pipeline and the two-stage pipeline, and a
comparator that compares a first output of the collapsible three-stage pipeline and a second output of the two-stage pipeline.