19 results about "PSoC" patented technology

The invention discloses a PSOC hardware platform design system based on optical fiber strapdown heading attitude, and the system comprises the steps: carrying out the circuit function module design based on a PSOC architecture, and enabling the circuit function module design to comprise a PSOC module and a power conversion circuit; a real-time operating system is operated on an ARM core of a PSOC, deployment of a service architecture is realized by utilizing a system calling interface provided by the operating system, the service architecture loosely couples application of a heading attitude product with interface communication, loosely couples bottom hardware with a user layer, initializes and starts a PSOC hardware platform system, and finally, the service architecture is connected with the PSOC. The operation of the servitization framework enhances the flexibility and maintainability of the system, and the system can better adapt to different demand changes through modular design and function extension.

The PSOC-based software computing GPU multi-path drawing method of the present application is suitable for image display of a multi-path airborne display system, and character images of any path are processed by a character picture generation module at the PS end and a video generation module at the PL end, and are output and displayed on a display of the airborne display system, greatly improving the integration of the system.

The invention provides a PSOC-based airborne display system, and belongs to the technical field of airborne display application, the PSOC-based airborne display system comprises a PSOC chip, a DDR3 memory module, a transceiver, an optical module and an Ethernet PHY, the PSOC chip comprises a PS part and a PL part which communicate with each other, the PS part is connected with the first DDR3 memory module, the transceiver and the Ethernet PHY, and the PL part is connected with the first DDR3 memory module, the transceiver and the Ethernet PHY. The PL part is connected with the second DDR3 memory module and the second optical module, and the first optical module is connected with the Ethernet PHY. A single PSOC is used as a main chip, airborne emergency graphics are drawn through an integrated CPU + GPU in the chip, integrated FPGA resources are used for avionics bus video decoding, video switching, video coding and transmitting display, and an integrated VPU compresses a display picture. The system integration level is improved, the weight and the size of a display product can be reduced, and the cost is reduced.

The invention discloses a JFMQL-based aviation airborne information processing board card, which comprises a JFMQL series PSoC chip, a DDR3 memory, a PCIe bridge chip and an external connector, the PL end of the JFMQL series PSoC chip is provided with a PCIe core, and the PCIe bridge chip is electrically connected with the PCIe core at the PL end of the JFMQL series PSoC chip and is electrically connected with the external connector; the DDR3 memory is electrically connected with the PSoC chip of the JFMQL series; and the PCIe core packages data to be interacted on the DDR3 memory into PCIe data according to a PCIe protocol, and the PCIe data are output to two external NVMe hard disks by the external connector through two paths of PCIe * 4 ports expanded by the PCIe bridge chip. According to the invention, the airborne communication rate can be effectively improved.

The invention provides a data transceiving and high-speed storage system based on a domestic PSOC (programmable system on chip), which comprises a PSOC control layer which takes a Feidan micro PSOC as a core arithmetic unit and provides bottom computing power support for efficient operation of the system by means of excellent hardware acceleration capability and flexible programmable characteristics; the high-speed data interaction layer carries a multi-protocol receiving and transmitting module composed of RS422, CANFD, 4M 1553B, a gigabit Ethernet and an optical module, can be compatible with multi-scene data transmission requirements, realizes high-speed stable receiving and transmitting of multi-type data, and breaks the bandwidth bottleneck; according to the high-speed data storage layer, EMMC, SATA and NVMe SSD multi-element media are creatively integrated, a hierarchical high-capacity high-speed storage architecture is constructed, the requirement for real-time storage of mass data is met, data calling instantaneity is guaranteed, and guarantee is provided for high-throughput scene data processing and storage. Through various communication protocols and various high-speed storage devices, the compatibility and universality of the control system are improved.

The utility model discloses an ultra-short wave module for communication of an unmanned vehicle, relates to the field of ultra-short wave modules, aims to solve the problems of large volume, complex structure and inconvenience in upgrading and updating in the prior art, and adopts the technical scheme that the ultra-short wave module comprises a bottom plate which is electrically connected with a core plate, a radio frequency plate and a bus interface; a chip and a memory are arranged on the core board, the memory is electrically connected with the chip, the chip is a programmable chip, and a digital signal processor and a radio frequency transceiver are further connected to the bottom board; and the bottom plate is also connected with a power amplifier unit. By adopting a zero-intermediate-frequency framework, the overall size is reduced, the overall power consumption is reduced, the reliability is remarkably improved, by adopting a PSOC (programmable system on chip), software can be repeatedly added and upgraded through a provided network port, devices do not need to be changed, and the expandability and the flexibility of the module are greatly improved.

The invention provides a dual-redundancy high-reliability computing device based on a PSOC. The dual-redundancy high-reliability computing device based on the PSOC comprises two PSOC computing units which are both in communication interaction with an avionics system through an FC bus; a dual-redundancy mechanism is realized between the two PSOC calculation units through a CCDL (Charge Coupled Device Language) protocol; the two PSOC computing units are respectively integrated with a 1394 bus daughter card, and the 1394 daughter card is used as a physical link for realizing a CCDL protocol between the two PSOC computing units; the two PSOC calculation units are respectively connected with a remote interface unit (RIU) through 1394 bus daughter cards, and are used for controlling execution mechanisms related to the remote interface unit (RIU) to execute service actions. According to the invention, the logic and physical interchangeability of the system is improved through the completely consistent dual-redundancy calculation unit design; the PSOC circuit is selected to realize integrated fusion of programmable logic and general calculation of the calculation unit, and the reliability and the energy consumption level of the system are improved; data communication and dual-redundancy function enabling realized by adopting a CCDL protocol provide an efficient path.

This invention provides a real-time image recognition system based on a PSoC chip, comprising: a CPU processor; a network model receiving module that receives configuration information and caches it in a first memory via the CPU processor; an image preprocessing module that receives acquired image data and preprocesses it according to the configuration information; a high-speed storage control module that caches the preprocessed image data in a second memory and retrieves the configuration information from the first memory via the CPU processor and caches it in the second memory; an AI acceleration hard core that retrieves the configuration information and preprocessed image data from the second memory via the high-speed storage control module, recognizes the image data based on a convolutional neural network model corresponding to the configuration information, and caches the recognition result in the second memory; and the high-speed storage control module sends the recognition result from the second memory to the first memory. This invention also provides a real-time image recognition method.

The invention provides a domestic PSOC-based program online upgrading system. The domestic PSOC-based program online upgrading system comprises an upper computer and terminal equipment, the upper computer comprises an upgrade program generation module and a communication module; the terminal equipment comprises a domestic PSOC platform, a FLASH memory, a DDR buffer and a terminal equipment communication module; the terminal equipment enters an upgrading state according to the upgrading instruction, and the PL program and the PS program running in the domestic PSOC platform are upgraded through the upgrading program. After the terminal equipment completes initialization, online program upgrading can be completed at any time, a special delay waiting module does not need to be arranged in the initialization stage to wait for an upper computer instruction, and the time constraint of online upgrading and the equipment starting time are reduced. The FLASH memory is provided with an independent factory program storage area and an independent upgrading program storage area, and after program upgrading fails, the FLASH memory can still be powered on to run factory programs. According to the method and the device, only single-partition data or multi-partition data needing to be upgraded can be upgraded online, so that the upgrading efficiency and the equipment maintainability are improved.

The invention relates to an information processing chip based on microsystem integration. A PSOC multi-core information processor bare core, a set of DDR3 bare cores, a set of Nor Flash bare cores, a high-precision LDO bare core and a reset bare core are installed on a switching substrate through the SiP technology. The DDR3 bare core is respectively hung on a PS end and a PL end of the PSOC multi-core information processor bare core to serve as a cache, and the FLASH bare core is respectively hung on a special pin of the PSOC and a PL Bank of the POC to serve as configuration file storage and solidification program and parameter storage of the PSOC or user customization; the LDO provides power supply voltage for the DDR3; and the reset chip bare chip monitors the working condition of the power supply voltage. The system has the advantages that miniaturization, low cost and low power consumption can be realized through a microsystem integration technology, and the system has rich logic resources and interfaces, high flexibility, strong universality and the like.

The invention relates to a high-reliability digital beam forming and controlling device which comprises two sub-modules, and the two sub-modules are consistent in board card framework and function and can be switched freely according to requirements. Each sub-module comprises a DBF subsystem, a system control subsystem and a configuration circuit subsystem, and each subsystem performs independent control of a power supply, a clock and reset; the configuration circuit subsystem is respectively connected with the DBF subsystem and the system control subsystem; the core component of the DBF subsystem is a V7 FPGA, the configuration circuit subsystem selects an anti-fuse type FPGA as a processor, and the system control subsystem selects a PSOC PGFA. According to the invention, through the redundant backup design, the main and standby modules are switched at will, including the external power supply and the clock, so that the robustness of key circuits of the equipment is improved, and the stability and reliability of the equipment are guaranteed through the reasonable structural design of multiple levels and multiple dimensions.

The invention relates to the technical field of signal acquisition, in particular to a remote interface state acquisition and control device based on a programmable logic component, the device takes a programmable fusion chip PSOC as a core board, and the programmable fusion chip PSOC is divided into a logic processing end and a system processing end; the logic processing end is used for completing analog quantity acquisition, analog quantity output, discrete magnitude acquisition, discrete magnitude output and protocol conversion among different types of interfaces; the system processing end communicates with the logic processing end through an AXI bus, and the system processing end is provided with a software system and used for controlling a remote interface and processing data. The system has the advantages of high reliability, high performance, low power consumption and programmable function, and realizes the integrated integration of information processing and control feedback.

The invention discloses a low-dropout linear regulator turn-off circuit for power-on of multiple power supplies in a PSoC (programmable system on chip). The low-dropout linear regulator turn-off circuit comprises a voltage domain switching circuit, a grid voltage control signal generating circuit and a power tube turn-off circuit. The voltage domain switching circuit is used for generating a cross-voltage domain power supply signal, the grid voltage control signal generation circuit is used for controlling the power tube turn-off circuit to ensure that the LDO is in a strict turn-off state in the RF-PSoC in the multi-power-supply power-on stage, and the situation that the LDO cannot be completely turned off by an enable signal due to multi-power-supply power-on in the PSoC is avoided.

The invention discloses a domestic PSOC mirror image partition storage and upgrading method based on secondary guidance, and belongs to the technical field of embedded software, the method comprises monitoring software and main control software, the monitoring software realizes online upgrading of ARM application software and FPGA application software through an ARM loading program; the main control software realizes the normal function of a product and the response of an online upgrading command, and a primary bootstrap program in the main control software is driven by bottom hardware to complete the initialization of basic hardware and the moving execution of a secondary bootstrap program; the second-level bootstrap program completes bootstrap starting of the ARM application software and the FPGA application software from different FLASH partitions, and the ARM application software and the FPGA application software complete product normal functions and response to online upgrading commands. According to the method, the workload of software development and maintenance is reduced, the reliability and safety of the system are improved, and the risks of mistaken updating and updating missing in software configuration item management are solved.

The invention provides a modular display control device and method based on FMQL. The display control device based on the FMQL comprises an FMQL series PSOC, a touch display screen, an NOR FLASH, an NAND FLASH, a DDR, a gigabit Ethernet, a serial port, a key and the like. The display and control method based on the FMQL comprises configuration of each interface controller of the system, transmission of data streams, analysis and storage of data, adaptation of an operating system, display and touch of an interface and the like. Based on the scheme, the modularized display control device and method based on the FMQL are realized, aiming at a scene with a display control requirement, resources required by display and partial control are allocated to the independent display control module, and the independent display control module can be used as an additional module to provide display and control services for any equipment with an RGMII protocol interface; due to the high-reliability design, the design can adapt to various complex and changeable scenes.

The invention discloses an LED numerical control constant current driving power supply with an improved structure, which comprises an input protection circuit, one end of the input protection circuit is connected with an EMI filter circuit, one end of the EMI filter circuit is connected with a rectification circuit, one end of the rectification circuit is connected with a manual encoder, one end of the manual encoder is connected with a PSoC chip, and the other end of the PSoC chip is connected with a power supply. One side of the PSoC chip is provided with an inductance matching unit, one end of the inductance matching unit is connected with an output rectification filter circuit, one end of the output rectification filter circuit is connected with an optocoupler feedback circuit, the circuit completes a constant current function, and the circuit is high in control precision from test data; from the test process, the circuit is stable and reliable, the phenomena of element damage and function failure do not occur after long-time work, and the circuit has short circuit and open circuit protection functions; the current fluctuation coefficient of the LED numerical control constant-current driving power supply is effectively reduced, the driving efficiency is higher, the circuit ensures the stability degree of current signal receiving of LED equipment, and the service life of an LED is prolonged.

The invention relates to an improved E1 link PTP (Precision Time Protocol) timing device. According to the device, a PSoC processor is selected, a PTP protocol is operated on a CPU at the PS end of the processor, an AXI 1G / 2.5 G Ethernet Subsystem IP core responsible for processing MAC of the Ethernet is used in a BD, and a PTP message receiving and sending processing module communicates with a GMII interface of the IP core through the GMII interface; the E1 transceiving processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and Ethernet data of a PTP message are sent in full time slots of an E1 link. PL logic resources are adopted in the PSoC processor to optimize hardware design of E1 link PTP time service, a physical Ethernet interface is not adopted for transmitting and receiving PTP messages through the processor, and the influence of uncertain transmitting and receiving delay of a PHY chip on time service precision is reduced.

The utility model discloses a digital-analog hybrid sip structure based on a software radio architecture, which relates to the technical field of electronics, and comprises a tube shell adopting a ceramic substrate double-sided design; wherein an SPI Flash is arranged on the TOP surface through lead bonding, and a multifunctional radio frequency chip and a PSOC chip are arranged on the TOP surface in an inverted manner; a DRAM (Dynamic Random Access Memory) chip is arranged on the Bottom surface through lead bonding; the SPI Flash, the DRAM chip and the multifunctional radio frequency chip are all connected with the PSOC chip; in the digital-analog hybrid sip structure, a software radio processing architecture of a PSOC chip and a multifunctional radio frequency chip is adopted, and a two-transmitting and three-receiving channel is established; the digital-analog hybrid system solves the problems that a conventional digital-analog hybrid system is large in overall size, poor in flexibility, single in use environment and the like, and meets the requirements of light weight, miniaturization and high reliability.

The application relates to an improved E1 link PTP timing device. The device selects a PSoC processor, a CPU at the PS end of the processor runs a PTP protocol, an AXI 1G / 2.5G Ethernet Subsystem IP core responsible for processing MAC of the Ethernet is used in the BD, a PTP message transceiving processing module communicates with a GMII interface and a GMII interface of the IP core; an E1 transceiving processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and full-time slot transmission of Ethernet data of the PTP message on the E1 link. The logic resource of PL is used in the PSoC processor to optimize the hardware design of the E1 link PTP timing, and the processor transceives the PTP message without using a physical Ethernet interface, so that the influence of transceiving delay uncertainty of the PHY chip on the timing accuracy is reduced.