10 results about "PSoC" patented technology

The PSOC-based software computing GPU multi-path drawing method of the present application is suitable for image display of a multi-path airborne display system, and character images of any path are processed by a character picture generation module at the PS end and a video generation module at the PL end, and are output and displayed on a display of the airborne display system, greatly improving the integration of the system.

The invention provides a data transceiving and high-speed storage system based on a domestic PSOC (programmable system on chip), which comprises a PSOC control layer which takes a Feidan micro PSOC as a core arithmetic unit and provides bottom computing power support for efficient operation of the system by means of excellent hardware acceleration capability and flexible programmable characteristics; the high-speed data interaction layer carries a multi-protocol receiving and transmitting module composed of RS422, CANFD, 4M 1553B, a gigabit Ethernet and an optical module, can be compatible with multi-scene data transmission requirements, realizes high-speed stable receiving and transmitting of multi-type data, and breaks the bandwidth bottleneck; according to the high-speed data storage layer, EMMC, SATA and NVMe SSD multi-element media are creatively integrated, a hierarchical high-capacity high-speed storage architecture is constructed, the requirement for real-time storage of mass data is met, data calling instantaneity is guaranteed, and guarantee is provided for high-throughput scene data processing and storage. Through various communication protocols and various high-speed storage devices, the compatibility and universality of the control system are improved.

The utility model discloses an ultra-short wave module for communication of an unmanned vehicle, relates to the field of ultra-short wave modules, aims to solve the problems of large volume, complex structure and inconvenience in upgrading and updating in the prior art, and adopts the technical scheme that the ultra-short wave module comprises a bottom plate which is electrically connected with a core plate, a radio frequency plate and a bus interface; a chip and a memory are arranged on the core board, the memory is electrically connected with the chip, the chip is a programmable chip, and a digital signal processor and a radio frequency transceiver are further connected to the bottom board; and the bottom plate is also connected with a power amplifier unit. By adopting a zero-intermediate-frequency framework, the overall size is reduced, the overall power consumption is reduced, the reliability is remarkably improved, by adopting a PSOC (programmable system on chip), software can be repeatedly added and upgraded through a provided network port, devices do not need to be changed, and the expandability and the flexibility of the module are greatly improved.

The invention provides a domestic PSOC-based program online upgrading system. The domestic PSOC-based program online upgrading system comprises an upper computer and terminal equipment, the upper computer comprises an upgrade program generation module and a communication module; the terminal equipment comprises a domestic PSOC platform, a FLASH memory, a DDR buffer and a terminal equipment communication module; the terminal equipment enters an upgrading state according to the upgrading instruction, and the PL program and the PS program running in the domestic PSOC platform are upgraded through the upgrading program. After the terminal equipment completes initialization, online program upgrading can be completed at any time, a special delay waiting module does not need to be arranged in the initialization stage to wait for an upper computer instruction, and the time constraint of online upgrading and the equipment starting time are reduced. The FLASH memory is provided with an independent factory program storage area and an independent upgrading program storage area, and after program upgrading fails, the FLASH memory can still be powered on to run factory programs. According to the method and the device, only single-partition data or multi-partition data needing to be upgraded can be upgraded online, so that the upgrading efficiency and the equipment maintainability are improved.

The invention relates to an information processing chip based on microsystem integration. A PSOC multi-core information processor bare core, a set of DDR3 bare cores, a set of Nor Flash bare cores, a high-precision LDO bare core and a reset bare core are installed on a switching substrate through the SiP technology. The DDR3 bare core is respectively hung on a PS end and a PL end of the PSOC multi-core information processor bare core to serve as a cache, and the FLASH bare core is respectively hung on a special pin of the PSOC and a PL Bank of the POC to serve as configuration file storage and solidification program and parameter storage of the PSOC or user customization; the LDO provides power supply voltage for the DDR3; and the reset chip bare chip monitors the working condition of the power supply voltage. The system has the advantages that miniaturization, low cost and low power consumption can be realized through a microsystem integration technology, and the system has rich logic resources and interfaces, high flexibility, strong universality and the like.

The invention relates to a high-reliability digital beam forming and controlling device which comprises two sub-modules, and the two sub-modules are consistent in board card framework and function and can be switched freely according to requirements. Each sub-module comprises a DBF subsystem, a system control subsystem and a configuration circuit subsystem, and each subsystem performs independent control of a power supply, a clock and reset; the configuration circuit subsystem is respectively connected with the DBF subsystem and the system control subsystem; the core component of the DBF subsystem is a V7 FPGA, the configuration circuit subsystem selects an anti-fuse type FPGA as a processor, and the system control subsystem selects a PSOC PGFA. According to the invention, through the redundant backup design, the main and standby modules are switched at will, including the external power supply and the clock, so that the robustness of key circuits of the equipment is improved, and the stability and reliability of the equipment are guaranteed through the reasonable structural design of multiple levels and multiple dimensions.

The invention discloses a low-dropout linear regulator turn-off circuit for power-on of multiple power supplies in a PSoC (programmable system on chip). The low-dropout linear regulator turn-off circuit comprises a voltage domain switching circuit, a grid voltage control signal generating circuit and a power tube turn-off circuit. The voltage domain switching circuit is used for generating a cross-voltage domain power supply signal, the grid voltage control signal generation circuit is used for controlling the power tube turn-off circuit to ensure that the LDO is in a strict turn-off state in the RF-PSoC in the multi-power-supply power-on stage, and the situation that the LDO cannot be completely turned off by an enable signal due to multi-power-supply power-on in the PSoC is avoided.

The invention discloses a domestic PSOC mirror image partition storage and upgrading method based on secondary guidance, and belongs to the technical field of embedded software, the method comprises monitoring software and main control software, the monitoring software realizes online upgrading of ARM application software and FPGA application software through an ARM loading program; the main control software realizes the normal function of a product and the response of an online upgrading command, and a primary bootstrap program in the main control software is driven by bottom hardware to complete the initialization of basic hardware and the moving execution of a secondary bootstrap program; the second-level bootstrap program completes bootstrap starting of the ARM application software and the FPGA application software from different FLASH partitions, and the ARM application software and the FPGA application software complete product normal functions and response to online upgrading commands. According to the method, the workload of software development and maintenance is reduced, the reliability and safety of the system are improved, and the risks of mistaken updating and updating missing in software configuration item management are solved.

The invention provides a modular display control device and method based on FMQL. The display control device based on the FMQL comprises an FMQL series PSOC, a touch display screen, an NOR FLASH, an NAND FLASH, a DDR, a gigabit Ethernet, a serial port, a key and the like. The display and control method based on the FMQL comprises configuration of each interface controller of the system, transmission of data streams, analysis and storage of data, adaptation of an operating system, display and touch of an interface and the like. Based on the scheme, the modularized display control device and method based on the FMQL are realized, aiming at a scene with a display control requirement, resources required by display and partial control are allocated to the independent display control module, and the independent display control module can be used as an additional module to provide display and control services for any equipment with an RGMII protocol interface; due to the high-reliability design, the design can adapt to various complex and changeable scenes.

The application relates to an improved E1 link PTP timing device. The device selects a PSoC processor, a CPU at the PS end of the processor runs a PTP protocol, an AXI 1G / 2.5G Ethernet Subsystem IP core responsible for processing MAC of the Ethernet is used in the BD, a PTP message transceiving processing module communicates with a GMII interface and a GMII interface of the IP core; an E1 transceiving processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and full-time slot transmission of Ethernet data of the PTP message on the E1 link. The logic resource of PL is used in the PSoC processor to optimize the hardware design of the E1 link PTP timing, and the processor transceives the PTP message without using a physical Ethernet interface, so that the influence of transceiving delay uncertainty of the PHY chip on the timing accuracy is reduced.