42results about How to "Improve Parallel Processing Efficiency" patented technology

A parallel data processing method based on multiple graphic processing units (GPUs) is provided, including: creating, in a central processing unit (CPU), a plurality of worker threads for controlling a plurality of worker groups respectively, the worker groups including a plurality of GPUs; binding each worker thread to a corresponding GPU; loading one batch of training data from a nonvolatile memory to a GPU video memory corresponding to one worker group; transmitting, between a plurality of GPUs corresponding to one worker group, data required by data processing performed by the GPUs through peer to peer; and controlling the plurality of GPUs to perform data processing in parallel through the worker threads.

A parallel data processing method based on multiple graphic processing units (GPUs) is provided, including: creating, in a central processing unit (CPU), a plurality of worker threads for controlling a plurality of worker groups respectively, the worker groups including one or more GPUs; binding each worker thread to a corresponding GPU; loading a plurality of batches of training data from a nonvolatile memory to GPU video memories in the plurality of worker groups; and controlling the plurality of GPUs to perform data processing in parallel through the worker threads. The method can enhance efficiency of multi-GPU parallel data processing. In addition, a parallel data processing apparatus is further provided.

The disclosure provides a request processing method and device, which belong to the technical field of computers. The method includes: acquiring a first request of a terminal; and assigning a lock to the first request based on the operation type and operation path corresponding to the first request when the first request meets the processing conditions, and the operation type refers to the operation type indicated by the first request. The type of operation to be performed, the operation path refers to the storage path of the operation object indicated by the first request; the operation corresponding to the first request is executed based on the lock; where the processing conditions include the operation corresponding to the first request and the operation corresponding to each second request No conflict; when the second request allocates a lock for the first request, the request has already been allocated a lock by the server. The present disclosure improves parallel processing efficiency.

The invention discloses a method, a device and a mobile terminal for checking the impact of cache file deletion. The method includes: obtaining a program to be checked, and obtaining a set of click paths and a set of cache paths corresponding to the program to be checked, wherein the set of click paths includes: Multiple click paths, the cache path set includes multiple cache paths, each click path set corresponds to a cache path; obtains a cache path to be verified in the cache path set, and deletes the cache path to be verified in the cache path to be verified file; simulate clicking on the program to be verified according to the click path corresponding to the cache path to be verified; and obtain the deletion effect of the cache file to be verified according to the running result of the program to be verified. The method of the embodiment of the present invention can realize automatic detection of whether the deleted cache file has an influence on the program only by simply adding equipment, thereby improving the parallel processing efficiency and reducing the labor cost.

The invention discloses a pipe-type communication method for interprocess communication, comprising the following steps: receiving the data processed by the process of a server at the previous level; caching the data to a first caching pool; reading the data in the first caching pool, and caching the data to a first memory buffer zone so as to bring convenience for the process of the server to process; writing the data processed by the process of the server into a second memory buffer zone; caching the data in the second memory buffer zone to the second caching pool; and sending the data in the second caching pool to the process of the server at the next level to process, wherein the first caching pool and the second caching pool are storage spaces arranged on an external memory. The invention also discloses a pipe-type communication system for interprocess communication. According to the method and the system, data in the pipe-type communication mode in the streamline concurrent processing process are cached by the large-capacity storage space of the external memory, thereby improving the reliability and the efficiency for data transmission during pipe-type communication.

The invention relates to a configurable matrix register unit for supporting multi-width single instruction multiple data stream (SIMD) and multi-granularity single instruction multiple threads (SIMT). The configurable matrix register unit comprises a matrix register and a control register SR; the matrix register of which the size is N*N is divided into M*M blocks, wherein N is a positive integer and is the power of 2, and M is an integer which is more than or equal to 0 and is the power of 2; the block modes of the matrix register and the multi-thread numbers simultaneously processed by a vector processing unit are recorded in the control register; and the width of the control register is log2C+log2T, wherein C is the number of the number of the block modes of the matrix register, and T is the number of multi-thread modes which can be processed by a vector processor. The configurable matrix register unit has the advantages that: the principle is simple; the configurable matrix register unit is simple and convenient to operate; the block size and the thread number can be configured flexibly; the access to vector data in the mode of multi-width SIMD and multi-granularity SIMT is supported at the same time and the like.

The invention relates to the field of parallel computation application technology and the field of high-performance scientific computation, in particular to an octree parallel construction method for visual reconstruction of CT slice data with a TB-level data processing ability. According to the method, octree parallel construction is performed based on an MPI+OpenMP parallel programming model by use of the characteristics of mesh generation of original volume data, non-dependency of octree node data, etc. based on the scheme of "construction on demand-Branch on need Octrees, BONOs" according to actual three-dimensional size of the volume data; on the one hand, waste of computation resources and storage resources and I / O expenditure in the construction process are reduced; and on the other hand, rapid octree data structure construction of the TB-level CT slice data is realized by means of parallel computation, and the MPI+OpenMP parallel programming technology meets the requirement for rapid construction of an octree data structural body of the TB-level CT slice data under different resolution requirements. The method has a good parallel speedup ratio and good parallel efficiency.

The invention discloses a method for maintaining a distributed dynamic two-layer forwarding table, including the training, query and aging process of the forwarding table. The training of the forwarding table includes: S1) external input of true random numbers; S2) receiving source address and Virtual local area network SA_vlan; S3) Hash the true random number and SA_vlan to calculate the address to be written; S4) The signal instruction of the entry corresponding to the address is transmitted downward; S5) If the entry to be written is set If it is invalid, the entry will not be written, otherwise, write SA_vlan into the entry in the sel circuit; S6) Hash the destination address DA_vlan and the true random number to obtain the address of the entry, and then read out the address to be queried forwarded port. Multiple small forwarding tables in the present invention adopt the same hash calculation rule, and form different hash maps with different true random numbers, so as to obtain a load rate much higher than that of a unified forwarding table, and greatly save FPGA Precious BRAM resources inside.

The invention provides an automobile chassis with an accumulated snow ball compressing transmission device, and belongs to the technical fields of environmental protection, mechanical transmission, road accumulated snow removal equipment and the like. An opening is formed in an automobile chassis body, the accumulated snow ball compressing transmission device is installed in the opening, and is composed of a snow ball integrating unit, an accumulated snow ball ejecting unit, an inclined plane transmission unit, a rolling wheel set, a snow ball integrating driving unit, a snow ball ejecting driving unit, a rolling wheel set driving unit and an accumulated snow ball collection unit. According to the automobile chassis with the accumulated snow ball compressing transmission device, the functions of transmission and collection of accumulated snow can be realized.