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2results about How to "Improve Parallel Processing Efficiency" patented technology

Packaging structure and data communication method for multi-stack high-bandwidth memory

PendingCN122086832AImprove memory access flexibilityImplement direct memory accessArchitecture with single central processing unitElectric digital data processingComputer hardwarePathPing
The embodiment of the invention provides a packaging structure of a multi-stack high-bandwidth memory and a data communication method. The packaging structure comprises a multi-layer internet, at least two high-bandwidth memory stacks and a path selection control unit matched with each high-bandwidth memory stack, the multi-layer internet is arranged between the at least two high-bandwidth memory stacks, and the path selection control unit is connected with the multi-layer internet; each high-bandwidth memory stack comprises a plurality of DRAM (Dynamic Random Access Memory) bare chips and a bottom logic bare chip which are vertically stacked; the multi-layer internet network comprises at least two transverse interconnection communication paths and is used for realizing data communication between the at least two high-bandwidth memory stacks; and the path selection control unit is configured to respond to a cross-stack target data access request, and select one target path from the at least two transverse interconnection communication paths according to a preset selection strategy to carry out target data transmission. By utilizing the packaging structure disclosed by the invention, the memory access flexibility and the parallel processing efficiency can be remarkably improved.
Owner:HANGZHOU WEIHENG TECHNOLOGY CO LTD

A method and system for additive manufacturing distributed equalization scanning

PendingCN122274218APrecisely balanced scan timesavoid waitingComputer hardwareGraphics
This invention relates to a distributed balanced scanning system and method for additive manufacturing, belonging to the field of additive manufacturing technology. The method includes: acquiring data information of the part to be processed, including data information of multiple slice layers; processing the data information to obtain initial graphic partition data; adjusting the initial graphic partition data, provided that the initial graphic partition data meets adjustment conditions, to obtain first target graphic partition data; re-estimating the total scanning time of each laser based on the first target graphic partition data, until the time difference between the total scanning times of the lasers is less than a time threshold or the number of iterations reaches a preset number, and obtaining second target graphic partition data; and allocating the second target graphic partition data to each laser for scanning and printing. This method achieves precise balancing of scanning time among multiple lasers, avoiding waiting and efficiency losses caused by uneven load, and significantly improving parallel processing efficiency.
Owner:FUJIAN INST OF RES ON THE STRUCTURE OF MATTER CHINESE ACAD OF SCI