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42results about How to "Improve Parallel Processing Efficiency" patented technology

Distributed real-time video monitoring processing system based on ZooKeeper

The invention discloses a distributed real-time video monitoring processing system based on a ZooKeeper. The system comprises video acquisition equipment, a ZooKeeper server farm, a memory database server, a real-time video processing server farm RVPS, a streaming media domain name service and a client. In the invention, the ZooKeeper server farm is used to realize high availability of a cluster, resource distribution and calculation and load balancing. The client sends an operation instruction to the real-time video processing server farm through the memory database server and can modify the operation instruction at any time. The RVPS accesses a real-time video stream from video acquisition equipment. Through polling a processing instruction stored in the memory database server, a real-time video is processed. The RVPS sends an original coded video to the client through an RTSP streaming media protocol and feeds back a processing result to the client through the memory database server so as to realize separation of the video and the processing result. The client accesses an RTSP video stream with an unchanged domain name and a changed IP address through the streaming media domain name service.
Owner:THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP

Maintenance method for distributed dynamic double-layer forwarding table

ActiveCN107171960ARealize the function of forwardingIncrease irrelevanceNetworks interconnectionForwarding planeReal-time computing
The invention discloses a maintenance method for a distributed dynamic double-layer forwarding table, and the method comprises the training, querying and aging process of a forwarding table, wherein the training process of he forwarding table comprises the steps: S1), inputting a real random number from the outside; S2), receiving a source address and a virtual local area network SA_vlan; S3), carrying out the Hash calculation of the real random number and the virtual local area network SA_vlan, and calculating a to-be-written address; S4), transmitting a signal indication of an item corresponding to the address downwards; S5), carrying out no writing of the item if a to-be-written item is set to be invalid, or else writing the virtual local area network SA_vlan into the item in an sel circuit; S6), carrying out the Hash calculation of a target address DA_vlan and the real random value, obtaining the address of the item, and reading a to-be-queried forwarding port. According to the invention, a plurality of small forwarding tables employ the same Hash calculation rule, and form different Hash mapping with different real random numbers. The item load rate which is far greater than the item load rate of one unified forwarding table is obtained, and the precious BRAM resources in an FPGA are greatly saved.
Owner:HUAXIN SAIMU CHENGDU TECH CO LTD

CUDA multi-thread processing method and system and related equipment

The invention provides a CUDA (Compute Unified Device Architecture) multi-thread processing method and system and related equipment, and the method comprises the following steps: obtaining configuration information corresponding to a kernel function; under the condition that the target historical configuration information matched with the configuration information does not exist in the historical configuration information, generating a three-dimensional index of the thread according to the configuration information; compressing and packaging the generated three-dimensional index according to the configuration information, and storing the compressed and packaged three-dimensional index in a memory; under the condition that the target historical configuration information exists in the historical configuration information, obtaining a historical three-dimensional index corresponding to the target historical configuration information; and compressing and packaging the historical three-dimensional index according to the target historical configuration information, and storing the compressed and packaged historical three-dimensional index in a memory. According to the embodiment of the invention, the multi-thread parallel processing efficiency in the CUDA can be improved.
Owner:AZURENGINE TECH ZHUHAI INC

Data area overlapped boundary data zero communication parallel computing method and system

The invention discloses a data area overlapped boundary data zero communication parallel computing method, which comprises the following steps of: partitioning mother data to be processed into a plurality of sub blocks of data, wherein each sub block of data stores boundary data of the adjacent sub block of data in a redundant way; and carrying out parallel processing to the sub blocks of data. The invention also discloses a data area overlapped boundary data zero communication parallel computing system, which comprises a data partitioning module which is used for carrying out redundant partitioning to the mother data, and a parallel processing unit which is used for carrying out parallel processing to the sub blocks of data, and also comprises a data partitioning module which is used for carrying out non-redundant partitioning to the mother data, a data exchange module which is used for exchanging the boundary data of the adjacent sub blocks of data and carrying out redundant storage to the boundary data, and a parallel processing unit which is used for carrying out parallel processing to the sub blocks of data. According to the method and the system, disclosed by the invention, the waiting time during the data transmission can be saved, and the efficiency of the parallel processing can be improved.
Owner:SHENZHEN INST OF ADVANCED TECH CHINESE ACAD OF SCI +1

Method and device for improving parallel processing efficiency of bare computer system, medium and equipment

The invention discloses a method and device for improving the parallel processing efficiency of a bare computer system, a medium and equipment, and belongs to the field of computer processing. The method comprises the following steps: transmitting current frame data containing N pieces of target information to a CPU (Central Processing Unit); processing first target information in the current frame data by utilizing the CPU; the hardware controller is used for sending the first target information, and meanwhile the CPU processes the second target information in the current frame data; and sending the ith target information of the current frame data by using the hardware controller, and judging whether the current frame data is processed or not, if the current frame data is judged not to be processed, continuing to process the (i + 1) th target information in the current frame data by the CPU, otherwise, starting to process the target information in the next frame data containing the M pieces of information by the CPU. According to the method and the device, the problems that CPU time is wasted when low-speed equipment sends data, and the overall task processing period is prolonged due to the fact that other work cannot be processed in parallel are solved.
Owner:北京木牛领航科技有限公司

Configurable matrix register unit for supporting multi-width SIMD and multi-granularity SIMT

The invention relates to a configurable matrix register unit for supporting multi-width single instruction multiple data stream (SIMD) and multi-granularity single instruction multiple threads (SIMT). The configurable matrix register unit comprises a matrix register and a control register SR; the matrix register of which the size is N*N is divided into M*M blocks, wherein N is a positive integer and is the power of 2, and M is an integer which is more than or equal to 0 and is the power of 2; the block modes of the matrix register and the multi-thread numbers simultaneously processed by a vector processing unit are recorded in the control register; and the width of the control register is log2C+log2T, wherein C is the number of the number of the block modes of the matrix register, and T is the number of multi-thread modes which can be processed by a vector processor. The configurable matrix register unit has the advantages that: the principle is simple; the configurable matrix register unit is simple and convenient to operate; the block size and the thread number can be configured flexibly; the access to vector data in the mode of multi-width SIMD and multi-granularity SIMT is supported at the same time and the like.
Owner:NAT UNIV OF DEFENSE TECH

A Parallel Octree Construction Method for Visual Reconstruction of CT Slice Data

ActiveCN106846457BMeet the purpose of 3D visualization reconstructionImprove the efficiency of serial number positioningImage memory managementProcessor architectures/configurationComputational scienceConcurrent computation
The invention relates to the field of parallel computation application technology and the field of high-performance scientific computation, in particular to an octree parallel construction method for visual reconstruction of CT slice data with a TB-level data processing ability. According to the method, octree parallel construction is performed based on an MPI+OpenMP parallel programming model by use of the characteristics of mesh generation of original volume data, non-dependency of octree node data, etc. based on the scheme of "construction on demand-Branch on need Octrees, BONOs" according to actual three-dimensional size of the volume data; on the one hand, waste of computation resources and storage resources and I / O expenditure in the construction process are reduced; and on the other hand, rapid octree data structure construction of the TB-level CT slice data is realized by means of parallel computation, and the MPI+OpenMP parallel programming technology meets the requirement for rapid construction of an octree data structural body of the TB-level CT slice data under different resolution requirements. The method has a good parallel speedup ratio and good parallel efficiency.
Owner:国家超级计算天津中心
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