Configurable matrix register unit for supporting multi-width SIMD and multi-granularity SIMT

Abstract

The invention relates to a configurable matrix register unit for supporting multi-width single instruction multiple data stream (SIMD) and multi-granularity single instruction multiple threads (SIMT). The configurable matrix register unit comprises a matrix register and a control register SR; the matrix register of which the size is N*N is divided into M*M blocks, wherein N is a positive integer and is the power of 2, and M is an integer which is more than or equal to 0 and is the power of 2; the block modes of the matrix register and the multi-thread numbers simultaneously processed by a vector processing unit are recorded in the control register; and the width of the control register is log2C+log2T, wherein C is the number of the number of the block modes of the matrix register, and T is the number of multi-thread modes which can be processed by a vector processor. The configurable matrix register unit has the advantages that: the principle is simple; the configurable matrix register unit is simple and convenient to operate; the block size and the thread number can be configured flexibly; the access to vector data in the mode of multi-width SIMD and multi-granularity SIMT is supported at the same time and the like.

Description

technical field [0001] The present invention mainly relates to the design field of vector registers in vector processors, in particular to a matrix register with configurable block size and thread number in vector processors to support single instruction stream multiple data streams (SIMD) and single The vector operation unit operating in the instruction stream multithreading (SIMT) mode performs multi-width and multi-granularity access to data. Background technique [0002] With the in-depth research of 4G wireless communication technology and video image processing technology, vector processors have been widely used. Rapidly evolving wireless communication protocols and video image processing algorithms require a large number of matrix operations, such as channel estimation, MIMO equalization, and DCT transformation. The parallel granularity of matrix operations in different algorithms is different, and the size of the matrix blocks processed by the algorithms is also dif...

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Problems solved by technology

[0005] Existing research provides access to block data of a fixed size in the above-mentioned matrix registers. These technologies read and write a row vector or a column vector of the matrix at a time. The length of the vector is fixed. When the length of the vector is greater than or less than the fixed length, Usually, multiple short vectors are combined into one long vector for parallel processing, or a long vector is split into several short vectors for step-by-step processing, which cannot flexibly handle matrix data of different sizes, and does not support multi-width SIMD processing. It also does not support simultaneous access to multiple matrix data in the form of multi-granularity SIMT, neither can obtain enough flexibility, nor can it develop enough parallelism, especially thread-level parallelism

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