4 results about "Single instruction, multiple threads" patented technology

This invention, belonging to the field of computational processing technology, proposes a method to accelerate sparse 3D convolution based on thread bundle alignment and memory access rearrangement. To address the issues of discontinuous memory access and low memory bandwidth utilization caused by the sparsity of convolution kernels in GPU architectures, this invention establishes a thread bundle aligned convolution kernel format method based on the direct convolution method. This method uses the width of the thread bundle as the basic unit for grouping and compression to obtain the thread bundle aligned convolution kernel format. Considering the single-instruction multithreading (SIMT) characteristics of graphics processors and the properties of convolution operations, this method is used to merge sparse convolution kernel data and perform vectorized memory access. A memory access conflict resolution rearrangement method is also established: Input data is stored in shared memory using a DHWC layout, and then a greedy algorithm is used to rearrange the weight storage order within each basic unit of the WAF, thereby eliminating shared memory conflicts for input data access by manipulating the address of each memory access.

A structured query language (SQL) query including an SQL intrinsic function is processed using native code including single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) processor instructions for execution on a processor having native parallelism. The native code is compiled from an implementation of the SQL intrinsic function in a platform-independent source code. The compiling comprises compiling the source code to generate a platform-independent intermediate representation (IR) of the source code. The IR is optimized for improved performance through parallelization. The optimized IR is lowered to generate the native code.

This application provides a branch execution method under a single-instruction multithreaded architecture and a general-purpose graphics processor. The method is applied to a general-purpose graphics processor (GPGPU), which includes a processing unit and a circuit unit. The method includes: the processing unit identifies a thread branch and acquires branch information, including a convergence point thread mask, a first branch count, a first branch thread mask, a second branch count, and a second branch thread mask; the processing unit inputs the branch information to the circuit unit, causing the circuit unit to complete a first setting, which includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to a first stack layer, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask; the processing unit executes a first target branch program; after the first target branch program is executed, the processing unit triggers the circuit unit to complete a second setting, which includes setting the program counter to the second branch count and the thread mask to the second branch thread mask based on the data saved in the first stack layer; the processing unit executes a second target branch program. By utilizing this branch execution method under the single instruction multithreaded architecture and the general-purpose graphics processor, good processing performance can still be maintained under the SIMT architecture with the low hardware complexity of GPGPU.

A Single Instruction Multiple Threads (SIMT) processor core comprising: (a) a configurable dataflow backend operative to support subword parallelism for execution of mixed-precision arithmetic operations, wherein the backend includes multiple dataflow network stages, each dataflow network stage including one or more functional units configurable to process multiple subwords within a register in parallel; (b) a configuration memory storing configuration data defining operational configurations of the dataflow network stages in the backend, wherein the configuration memory is accessible via a configuration index mechanism operative to select configuration data from the configuration memory to control the dataflow network stages in the backend, and wherein the configuration index mechanism is configured for enabling the dataflow backend to support multiple variations of mixed-precision arithmetic operations without requiring dedicated instructions for each variation.