16 results about "Single instruction, multiple threads" patented technology

Techniques are disclosed relating to accessing source data in single-instruction multiple-thread (SIMT) pipelines. In some embodiments, multiple categories of operand resource circuits are configured to provide operands for instructions executed by processor pipeline circuitry. Per-resource arbitration circuitry may arbitrate between the SIMT execution slots for access to different operand resources. Source access circuitry may access operand data from operand resources based on source capture commands and source control circuitry may prior to a first SIMT group winning arbitration for all its operands, send a source capture command to the source access circuitry in response to the first SIMT group winning arbitration at the per-resource arbitration circuitry for a first operand resource. Instruction control circuitry may send an instruction release command down the processor pipeline circuitry for the first SIMT group, in response to the first SIMT group winning arbitration for all its operands.

The disclosed method for rendering graphic images includes, for each lane contained in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane contained in the plurality of lanes, computing a filtered value based on a plurality of the texel samples read from a corresponding plurality of lanes, based on a footprint associated with the lane; and rendering at least one section of a graphic image based on the filtered values ​​computed for the plurality of lanes.

The invention relates to the technical field of SRAM (Static Random Access Memory) in-memory computing, in particular to a single-instruction multi-thread SRAM in-memory computing unit control system. According to the invention, a single instruction multithreading (SIMT) control flow is used for controlling a computing unit in a static random access memory (SRAM). Compared with a traditional single instruction multiple data (SIMD) control flow, the SIMT control flow is higher in flexibility, the control granularity of a computing unit is smaller, and programming and control unit design are facilitated. By using the SIMT control flow, the idle running of the calculation column can be remarkably reduced, so that the calculation efficiency is improved and the energy consumption is reduced. Meanwhile, the whole computing architecture can be divided into a plurality of relatively independent computing cores by using the SIMT control flow for control, so that the centrality and explosiveness of storage access are reduced.

The invention provides an instruction fetching request processing method and device and a single-instruction multi-thread processor, and belongs to the technical field of computers.The method comprises the steps that after instruction fetching requests of thread bundles are received each time, instructions corresponding to the instruction fetching requests are searched in a preset first table item; returning the instruction searched in the first table item to the corresponding thread bundle; if the corresponding instruction is not found in the first table item, sending a target request to an instruction cache once; the target requests are instruction fetching requests of which the corresponding instructions are not found in the first table item, and the physical addresses of the target requests are the same; instructions returned by the instruction cache are returned to the thread bundles corresponding to the target requests, and the target data are stored in the first table item; the target data comprises an instruction returned by the instruction cache. According to the invention, the cache occupied by the instruction fetching request can be greatly reduced.

This invention, belonging to the field of computational processing technology, proposes a method to accelerate sparse 3D convolution based on thread bundle alignment and memory access rearrangement. To address the issues of discontinuous memory access and low memory bandwidth utilization caused by the sparsity of convolution kernels in GPU architectures, this invention establishes a thread bundle aligned convolution kernel format method based on the direct convolution method. This method uses the width of the thread bundle as the basic unit for grouping and compression to obtain the thread bundle aligned convolution kernel format. Considering the single-instruction multithreading (SIMT) characteristics of graphics processors and the properties of convolution operations, this method is used to merge sparse convolution kernel data and perform vectorized memory access. A memory access conflict resolution rearrangement method is also established: Input data is stored in shared memory using a DHWC layout, and then a greedy algorithm is used to rearrange the weight storage order within each basic unit of the WAF, thereby eliminating shared memory conflicts for input data access by manipulating the address of each memory access.

The invention provides an error detection method and system for a single-instruction multi-thread processor, electronic equipment and a medium. The method comprises the steps that the number of active threads and the number of inactive threads in a current thread bundle of the single-instruction multi-thread processor are counted; the number of the active threads is compared with the number of the inactive threads, when the number of the active threads is larger than the number of the inactive threads, thread recombination operation is triggered, the current thread bundle is updated, and a new thread bundle is obtained; the number of new active threads in the new thread bundle is smaller than or equal to the number of new inactive threads; based on a new inactive thread in the new thread bundle, performing redundancy calculation on a calculation task of a new active thread in the new thread bundle to obtain a first redundancy calculation result; and comparing the first original calculation result of the new active thread in the new thread bundle with the first redundancy calculation result, and performing error detection based on the first comparison result. Through thread recombination and redundancy calculation, the error detection cost is reduced, and the resource utilization rate is increased.

The disclosed method for rendering graphic images includes, for each lane contained in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane contained in the plurality of lanes, computing a filtered value based on a plurality of the texel samples read from a corresponding plurality of lanes, based on a footprint associated with the lane; and rendering at least one section of a graphic image based on the filtered values ​​computed for the plurality of lanes.

The disclosed method for rendering graphics images includes, for each lane included in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane included in the plurality of lanes, computing a filtered value based on a plurality of the texel samples that are read from a corresponding plurality of lanes based on a footprint associated with the lane; and rendering at least one portion of a graphics image based on the filtered values computed for the plurality of lanes.

A structured query language (SQL) query including an SQL intrinsic function is processed using native code including single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) processor instructions for execution on a processor having native parallelism. The native code is compiled from an implementation of the SQL intrinsic function in a platform-independent source code. The compiling comprises compiling the source code to generate a platform-independent intermediate representation (IR) of the source code. The IR is optimized for improved performance through parallelization. The optimized IR is lowered to generate the native code.

This application provides a branch execution method under a single-instruction multithreaded architecture and a general-purpose graphics processor. The method is applied to a general-purpose graphics processor (GPGPU), which includes a processing unit and a circuit unit. The method includes: the processing unit identifies a thread branch and acquires branch information, including a convergence point thread mask, a first branch count, a first branch thread mask, a second branch count, and a second branch thread mask; the processing unit inputs the branch information to the circuit unit, causing the circuit unit to complete a first setting, which includes saving the convergence point thread mask, the second branch count, and the second branch thread mask to a first stack layer, setting the program counter to the first branch count, and setting the thread mask to the first branch thread mask; the processing unit executes a first target branch program; after the first target branch program is executed, the processing unit triggers the circuit unit to complete a second setting, which includes setting the program counter to the second branch count and the thread mask to the second branch thread mask based on the data saved in the first stack layer; the processing unit executes a second target branch program. By utilizing this branch execution method under the single instruction multithreaded architecture and the general-purpose graphics processor, good processing performance can still be maintained under the SIMT architecture with the low hardware complexity of GPGPU.

A processor of an aspect includes a banked memory. The banked memory has a plurality of memory banks. The processor also includes a single instruction, multiple thread (SIMT) processor. The SIMT processor includes a plurality of processor elements. The processor elements are to perform memory access operations with memory addresses. The processor also includes banked memory access circuitry coupled with the banked memory, and coupled with the SIMT processor. The banked memory access circuitry is to access data in the banked memory with each of the memory addresses. The banked memory access circuitry is reconfigurable during runtime to map the memory addresses to the memory banks in a plurality of different ways. Other processors, methods, systems, and non-transitory machine-readable storage mediums are also disclosed.

A tool analyzes source code of a program that targets a parallel processing system, and searches for parallelism unstructured behavior values that potentially inhibit parallelism efficiency. Example parallelism unstructured behavior values include particular memory addresses, memory masks, control divergences, and instruction predicates, which are identified according to their context and use in the program. The tool also locates program operations that contribute to these values, and determines a source of parallelism structure information in the program. In some scenarios, the tool populates a pattern data structure which is suitable to help guide code generation. Patterns detected include addressing patterns, mask patterns, and thread control patterns. Programs analyzed include single instruction multiple data programs and single instruction multiple thread programs. Code generation guided by the pattern data structure to optimize parallelism efficiency produces smaller and faster program code which consumes less on-chip memory.

The disclosed method for rendering graphics images includes, for each lane included in a plurality of lanes in a wave, sampling a texel based on a filter to generate a texel sample; for each lane included in the plurality of lanes, computing a filtered value based on a plurality of the texel samples that are read from a corresponding plurality of lanes based on a footprint associated with the lane; and rendering at least one portion of a graphics image based on the filtered values computed for the plurality of lanes.

A Single Instruction Multiple Threads (SIMT) processor core comprising: (a) a configurable dataflow backend operative to support subword parallelism for execution of mixed-precision arithmetic operations, wherein the backend includes multiple dataflow network stages, each dataflow network stage including one or more functional units configurable to process multiple subwords within a register in parallel; (b) a configuration memory storing configuration data defining operational configurations of the dataflow network stages in the backend, wherein the configuration memory is accessible via a configuration index mechanism operative to select configuration data from the configuration memory to control the dataflow network stages in the backend, and wherein the configuration index mechanism is configured for enabling the dataflow backend to support multiple variations of mixed-precision arithmetic operations without requiring dedicated instructions for each variation.

Systems and methods are described herein for a list-based single-instruction, multiple-thread (SIMT) processing system. The list-based SIMT system executes a program across many threads by organizing threads into variable-length thread lists. Each thread list includes thread contexts and a program counter common to the thread list. The system includes a scheduler to select thread lists, an instruction handler to fetch and decode using the program counter, and execution hardware to apply the decoded instruction one thread context at a time. A list manager handles divergence by dividing diverging thread contexts of a thread list into two or more child thread lists for different next program counters. The list manager also performs reconvergence by merging thread lists that satisfy a reconvergence condition.

A system for compiling or running a data-parallel program with split-union using function calls, including: a SIMT processor (100) with a pipeline control unit (108); a partition unit configured to divide strand groups of the SIMT processor (100) into a parent group and at least one worker group prior to compilation or runtime execution of the data-parallel program; and a string allocation unit that is connected to and configured with the partition unit to determine one of the strings from the parent group to be executed as the parent string and to determine all strings in the at least one worker group to be executed as worker strings before compiling or running the data-parallel program, where the parent strand of the parent strand group operates on the SIMT processor during a sequential phase of the data-parallel program, the worker strands of the worker group operate during a parallel phase of the data-parallel program on the SIMT processor, The higher-level strand waits until the parallel phase is completed. Other strands of the parent group remain inactive during the data-parallel program, and The system configures a shared memory (110) of the SIMT processor to identify a running task.