Integrated circuit static time sequence analysis method for GPU accelerated calculation

Abstract

The invention discloses an integrated circuit static time sequence analysis method for GPU accelerated calculation. The method comprises the steps that: RC time delay is calculated and delayed updating is performed; input circuit information is expressed as a circuit structure diagram, flattening is conducted on the circuit structure diagram, the edge relation in the circuit structure diagram is expressed as a father node pointer or a compression adjacency list, a dynamic planning and topological sorting algorithm on the circuit structure diagram is designed, and a GPU algorithm for static timing sequence analysis of an integrated circuit is designed; and the GPU algorithm conforms to a single-instruction multi-thread architecture, so that the time of CPU-GPU computing tasks is merged. Byadopting the technical scheme provided by the invention, the static time sequence analysis cost of the integrated circuit can be reduced, and the performance of a time sequence driven chip design automation algorithm is further improved.

Description

technical field [0001] The invention belongs to the field of integrated circuit design automation, and relates to an integrated circuit static timing analysis method for GPU accelerated calculation, in particular to the parallel processing of algorithm steps in the static timing analysis process in integrated circuit back-end design and accelerated calculation using GPU Methods. Background technique [0002] In sequential logic chip design, every rising edge of the clock, the register in the integrated circuit will store the data at the input end, and the output end of the register and the input end of the register for the next calculation step are connected by combinational logic. According to different specifications, the register has requirements for the data preparation time of the input terminal. Before the rising edge of the clock arrives, the data at the input terminal must remain stable; after the rising edge of the clock arrives, the data at the input terminal must ...

AI Technical Summary

Problems solved by technology

However, this kind of method is limited by the huge overhead of thread switching on the CPU, as well as the uncoordinated and irregular computing modes between threads. The acceleration effect will be saturated when 8 to 16 cores are used, and more cores cannot be used to achieve greater performance. speedup ratio

[0007] (2) The traditional GPU-based static timing analysis acceleration method only accelerates the "delay propagation" step in the timing analysis step, while other steps such as "RC delay calculation" and "circuit structure diagram hierarchical pre-processing" are accelerated. Processing" takes up most of the time of the entire timing analysis flow, these steps are still running on the CPU, and efficient GPU algorithms are not designed for it

[0008] (3) For the "delay propagation" step already running on the GPU, considering the data format conversion between the CPU and the GPU, and the time for data copying between the main memory and the video memory, the traditional acceleration work cannot be significantly improved Provides a performance boost, sometimes even a drop in performance

For example, the work published by Murray et al. on FPT shows that considering the core computing time alone, the computing time of "delay propagation" running on the GPU is 6.2 times faster than that of the CPU, but the data copying time between the CPU and the GPU cannot Omitted, after adding this part of the overhead, the GPU is slower than the CPU

[0009] To sum up, the existing static timing analysis acceleration methods are limited by the shortcomings of CPU multi-threading, do not make full use of the hardware acceleration potential of GPU, and lack the ability to accelerate the entire timing analysis process, so they cannot achieve good performance. promote

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