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Single-instruction multi-thread staining cluster structure of uniform staining architecture graphics processor

A graphics processor and single-instruction technology, applied in the direction of processor architecture/configuration, concurrent instruction execution, electrical digital data processing, etc., can solve poor portability, security, reliability, guarantee hidden dangers, and restrict the independent development of display systems and other problems, to achieve the effect of powerful computing power and powerful unified dyeing ability

Active Publication Date: 2017-05-10
XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Especially in the field of military use, foreign imported commercial GPU chips have hidden dangers in safety, reliability, security, etc., and cannot meet the needs of the military environment; "Blocking" and product "monopoly" make it difficult to obtain the underlying technical information of the GPU chip, such as register information, detailed internal micro-architecture, core software source code, etc., resulting in the inability of GPU functions and performance to be fully utilized, and poor portability; the above problems are serious Restricting the independent development and independent development of my country's display system, it is imminent to develop a unified dyeing graphics processor chip with independent intellectual property rights, and the single-instruction multi-threaded dyeing cluster is the key and core of the unified dyeing array unit in the unified dyeing graphics processor. It is urgent to conduct research and breakthroughs in its design technology

Method used

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  • Single-instruction multi-thread staining cluster structure of uniform staining architecture graphics processor
  • Single-instruction multi-thread staining cluster structure of uniform staining architecture graphics processor
  • Single-instruction multi-thread staining cluster structure of uniform staining architecture graphics processor

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Embodiment

[0055] SSC is the main component of the unified coloring array, the main functional component for vertex and pixel coloring, and the hardware carrier for warp execution. Warp is a collection composed of data to be processed, programs for processing data, and result data after processing. Multiple warps can be executed in time-sharing on the same SSC hardware without interfering with each other. Different warps need to have different on-site record related information, that is, warps need to be supported by corresponding hardware. On SSC: warp data to be processed consists of 16 vertices or pixels that need to be processed in the same way (vertex coloring or pixel coloring); programs for processing data include two categories, namely vertex coloring programs and pixel coloring programs; The resulting data includes vertex-colored output and pixel-colored output. One SSC supports 8 warps, and the SSC can select one of the 8 warps per cycle, and uses dual-issue technology to issu...

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PUM

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Abstract

The invention belongs to the field of graphics processor design, and relates to a single-instruction multi-thread staining cluster structure of a uniform staining architecture graphics processor. The structure comprises a CU (Control Unit) (3), a FDU (Fetch Decode Unit) (2), an I$ (Instruction Cache) unit (4), a plurality of SPUs (Staining Processing Unit) (1), a SSRAM (Synchronous Static Random Access Memory) unit (8), a RAC (RAM Access Control) unit (7), a LSU (Load Storage Unit) (6) and a C$ (Constant Cache) unit (5), wherein the CU (3) is used for controlling and scheduling SSC; the FDU (2) is used for carrying out FD on an instruction; the I$ unit (4) is used for quickening an instruction access speed; the SPUs are used for executing a staining program; the SSRAM unit (8) is used for sharing data among the SPUs; the RAC unit (7) is used for carrying out decoding and arbitration control on internal memory access; the LSU (6) is used for carrying out data exchange among the SSRAM unit (8), the internal memories of the SPUs and a RF (Radio Frequency) unit; and the C$ unit (5) is used for quickening constant access. By use of the structure, a single-instruction multi-thread processing way is realized.

Description

technical field [0001] The invention belongs to the design field of graphic processors, and relates to a single-instruction multi-thread dyeing cluster structure of a graphic processor with a unified dyeing architecture. Background technique [0002] Graphics processor (Graphic Process Unit, GPU) is an important part of modern computer hardware, and it is a key component for graphics drawing, processing and display. system. The GPU is responsible for generating 2D and 3D graphics, images, and videos to support visual computing such as window-based operating systems, graphical user interfaces, video games, visual image applications, and video playback. The development of GPU technology has mainly gone through the stages of fixed-function pipeline, separated shader architecture, and unified shader architecture. Its graphics processing capability has been continuously improved, and its application field has gradually expanded from the initial graphics drawing to the general co...

Claims

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Application Information

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IPC IPC(8): G06T1/20G06F9/38
CPCG06F9/3887G06T1/20
Inventor 田泽任向隆张骏韩立敏马城城郑新建
Owner XIAN AVIATION COMPUTING TECH RES INST OF AVIATION IND CORP OF CHINA
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