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Single-Instruction-Multiple-Treads (SIMT) computing system and method thereof

A computing system and multi-threading technology, applied in the field of vector processing, can solve problems such as low efficiency utilization, and achieve the effect of improving system performance

Active Publication Date: 2016-12-28
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, only one control flow path can be executed at a time, even if that control flow path is not available to other threads
In addition, redundant bookkeeping of threads (redundant bookkeeping) can also cause inefficient utilization

Method used

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  • Single-Instruction-Multiple-Treads (SIMT) computing system and method thereof

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Embodiment Construction

[0019] In the following description, a lot of specific details will be listed. However, it should be understood that the embodiments of the present invention can also be implemented without these specific details. In other cases, in order to explain the idea of ​​the present invention more clearly, the present invention does not describe well-known circuits, structures and technologies in detail. However, those skilled in the art can understand that the present invention can be implemented without these specific details. And after reading the specification of the present invention, those skilled in the art can realize the present invention without too much experiment.

[0020] The embodiments of the present invention provide a method and system for improving the efficiency of a SIMT computing system by performing scalar processing on multi-threaded vector processing. If a set of threads (ie, a thread block) of an instruction has the same source operand (and therefore has the sa...

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Abstract

The invention provides a Single-Instruction-Multiple-Treads (SIMT) computing system including multiple processors and a scheduler to schedule multiple threads to each of the processors. Each processor includes a scalar unit to provide a scalar lane for scalar execution and vector units to provide N parallel lanes for vector execution. During execution time, a processor detects that an instruction of N threads has been predicted by a compiler to have (N M) inactive threads and the same source operands for M active threads, where N>M>=1. Upon the detection, the instruction is sent to the scalar unit for scalar execution. The single-instruction-multiple-treads computing system can improve the performance of the system.

Description

Technical field [0001] The present invention relates to a vector processing method, and more specifically, to a vector processing method in a single-instruction-multiple-thread (Single-Instruction-Multiple-Thread, hereinafter referred to as SIMT) computing system. Background technique [0002] Single instruction multithreading is a parallel execution mode adopted by some current graphics processing units (hereinafter referred to as GPU). This GPU can use multiple parallel data paths to execute a single instruction on multiple threads simultaneously in a lock-step manner. Single-Program-Multiple-Data (SPMD) accelerator language has been developed and designed, such as with It can be used to improve the computing performance of a GPU with a SIMT architecture. [0003] Some current GPUs can execute a single instruction on more threads than parallel data paths. For example, a processor with 32 parallel data paths can execute one instruction on 128 threads in 4 consecutive cycles. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3887G06F9/3851
Inventor 张嘉洋
Owner MEDIATEK INC
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