30results about How to "With programmable" patented technology

The invention discloses an integrated circuit structure special for a specific application algorithm. The structure comprises at least one processor which can be configured with an operational unit, and at least one processor which can be configured with a storage component, wherein the processor which can be configured with the operational unit or the processor which can be configured with the storage component is mutually connected with at least one of the processor which can be configured with the operational unit and the processor which can be configured with the storage component; the processor which can be configured with the operational unit comprises a first algorithm data control component and at least one operational unit, and the first algorithm data control component executes a configuration instruction and configures the operation function of the operational unit; and the processor which can be configured with the storage component comprises a second algorithm data control component and at least one storage component, and the second algorithm data control component executes the configuration instruction and configures the storage function of the storage component. Thestructure has the advantages of flexibility of configurability and programmability, simple and convenient operation, and good algorithm confidentiality.

The invention discloses a sweep signal generator, which comprises a parameter command receiving port, a sweep frequency control parameter generating unit, a sweep frequency control word random access memory (RAM), an RAM read address generator, a parameter regulating unit, a phase accumulator, a carrier address accumulator, a carrier sheet RAM, an adder, an analog-digital converter and a low pass filter. A method of superposing two paths of frequency components is adopted, namely a method for adding a frequency base unit weight part of a sweep signal and a frequency increment part of the sweep signal is utilized to generate the sweep signal, and the accuracy and frequency resolution of the generated sweep signal are greatly improved. The sweep signal generator has the highest accuracy of 1uHz. Moreover, a digital signal processor (DSP), a field programmable gate array (FPGA) and other digital processing modes are adopted, so the characteristics of programmability and high speed are achieved, the DSP, FPGA and the like can be integrated on a printed circuit board (PCB) and are not required to be connected through extra connecting lines, and the external interference can be reduced.

The invention discloses a novel electric water pump, and the novel electric water pump comprises a motor and a water pump, the motor is fixedly connected to the water pump, the motor comprises a drive part and a control part, the control part comprises a fixing shell, a chip plate is formed in the fixing shell, the chip plate is fixedly connected to the fixing shell, the chip plate is provided with an integrated chip, the integrated chip is fixedly connected to the chip plate, the drive part comprises a brushless stator and a brushless rotor, the brushless stator is sleeved out the brushless rotor. The novel electric water pump has the characteristic of compact structure, reliable and simple use, low noise, saving on energy and environment friendly, intelligent control and programming, also has the function of water out protection, overload protection, reverse connection protection and speed adjustment, the fault of the pump can be reduced, the use efficiency and reliability of the novel pump can be raised and the water pump and the motor can be effectively protected.

The invention discloses a deep packet detection system and method based on a software defined network, and relates to the field of deep packet detection. The deep packet detection system includes network equipment which supports a DPI function, a DPI controller and a DPI server, wherein the network equipment which supports the DPI function is used for processing the part of the second layer to the fourth layer of a deep packet detection rule, the DPI server is used for processing the part above the fourth layer of the deep packet detection rule, and the DPI controller is used for controlling and coordinating the whole deep packet detection system, including the steps of synchronizing flow tables, configuring the network equipment which supports the DPI function and the deep packet detection rule on the DPI server, and coordinating the network equipment which supports the DPI function and the DPI server. The deep packet detection system based on the software defined network can improve the utilization rate of resources, and can also realize effective control of a DPI system, and the functions and performance of the DPI system are enhanced.

The embodiment of the invention provides a data transmission system and a programmable serial peripheral interface controller. The data transmission system comprises a serial peripheral interface and a programmable controller. The serial peripheral interface is coupled between a first device and at least one second device. The programmable controller is used for controlling the serial peripheral interface to be switched between a single-port data transmission mode and a multi-port data transmission mode, wherein when more than one second device is coupled to the serial peripheral interface, the serial peripheral interface is switched to the multi-port data transmission mode and used for controlling multi-port data transmission between the first device and the second device, the first device simultaneously transmits data to each second device through a first transmission bus end of the serial peripheral interface, and the first device simultaneously receives data from each second device through a second transmission bus end of the serial peripheral interface.

The invention discloses an FPGA based multi-board-card array parallel decoding device and method. The device, adopting a CPCI communication framework, comprises a main control card used for communicating with the exterior and carrying out management scheduling control for a decoded card, more than six decoding cards used for decoding fast operation and reporting an operation result and a back plate used for the decoding cards and the main control card to finish high-speed interconnection of the board cards; the parallel decoding device adopts an ARM processor to take charge of state management inside each board card and configuration uploading of am FPGA firmware, and transmits the state information to a PC (Principal Computer) through an internal network path; and the PC controls and schedules based on related states. The decoding device makes a full use of the high-speed serdes interface of the FPGA, so that the data transmission bandwidth is improved and the data transmission time is reduced; and each board card is internally provided with a high-speed big-capacity memory DDR3 unit, so that high-speed storage and access of data is guaranteed.