Design method for calibration circuits for pipeline ADCs

Abstract

The invention relates to the technical field of analog integrated circuits, more particularly to a design method for calibration circuits for pipeline ADCs. The method is performed through the following steps: building a behavior level model for a pipeline ADC and establishing a quantification relation between the design parameters of an ADC analog circuit and the design parameters of a digital calibration circuit on one hand and the ADC performances on the other hand; obtaining the design parameters of both the analog circuit and the digital calibration circuit, with which least power will be consumed from the ADC; designing circuits according to the obtained parameters; obtaining calibration coefficients by a calibration algorithm and referring to a DAC; and writing the calibration coefficients into the calibration circuits. With the method provided by the invention, a calibration circuit can be simplified a lot. In addition to that, as all work is done on a chip, less power and space are required. Compared to a back-ground calibration circuit on a traditional chip, up to 50% of power and space are saved. A calibration circuit requires an increase in size and power consumption only of the ADC core by 10% and 5% respectively with no increase in the size and power consumption of the chip. Further, the calibration system can be adapted for different working environments.

Description

technical field [0001] The invention relates to the technical field of analog integrated circuits, in particular to a calibration circuit design method for pipeline ADCs. Background technique [0002] ADC converts analog signals into digital signals, and is widely used in various electronic systems such as communication, signal processing, and storage, and plays an irreplaceable role. At present, with the rapid development of electronic information technology, the market urgently needs high-speed, high-precision, low-voltage and low-power ADCs that can be integrated with digital circuits. Pipeline ADC has become the focus and hotspot of research at home and abroad because of the good compromise between speed, precision and power consumption. [0003] The conversion accuracy of the pipeline ADC is affected by many errors in the circuit, mainly including: thermal noise, clock jitter, switch on-resistance non-linearity, capacitance mismatch, operational amplifier (hereinafter ...

AI Technical Summary

Problems solved by technology

[0005] At present, the present invention proposes a calibration circuit design with low power consumption, on-chip integration (SoC) and programmable calibration coefficients in order to solve the problems of too much power consumption, too complicated implementation and too slow calibration speed of the above-mentioned existing calibration circuit method

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