Self-adaptation method for back-propagation (BP) nerve cell with multilayer structure

A neuron self-adaptive, multi-layer structure technology, applied in the field of self-adaptation, can solve the problems such as the inability of the calculation speed to meet the real-time requirements, the poor flexibility of hardware implementation, and the low degree of parallelism.

Inactive Publication Date: 2011-04-06
FUJIAN NORMAL UNIV
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Problems solved by technology

However, the main problem of the traditional general-purpose processor-based software implementation method is that the degree of parallelism is low, especially in the field of embedded applications, and the calculation

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  • Self-adaptation method for back-propagation (BP) nerve cell with multilayer structure
  • Self-adaptation method for back-propagation (BP) nerve cell with multilayer structure
  • Self-adaptation method for back-propagation (BP) nerve cell with multilayer structure

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Embodiment Construction

[0022] A kind of programmable hardware BP neuron processor 12 provided by the present invention consists of a local data bus 1, a special register group 2, a control register group 3, an arithmetic unit 4, a weight memory 5, an error transfer factor memory 6, and the number of weights Counter 7, layer number counter 8, training batch counter 9, microcontroller 10 and external control bus 11 constitute.

[0023] The special register group 2 , the control register group 3 , the arithmetic unit 4 , the weight memory 5 , and the error transfer factor memory 6 are respectively connected to the local data bus 1 .

[0024] Described micro-controller 10 and special-purpose register group 2, control register group 3, arithmetic unit 4, training batch counter 9, layer number counter 8, error transfer factor memory 6, weight memory 5, weight number counter 7 There is a connection.

[0025] The control register group 3 is composed of a control word register 20 and eight neuron number reg...

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Abstract

The invention relates to the field of nerve network hardware realization, in particular to a self-adaptation method for the computation of a single nerve cell node in a BP nerve network with a multilayer structure in different computation stages to realize different learning algorithm. A nerve cell processor is used for executing the computation of the single node on each layer of the BP nerve network. By programming a control register, a microcontroller can control an arithmetic device to execute the computation of three different kinds of BP nerve networks at the nerve cell node, wherein BP nerve network learning algorithm includes three kinds of typical learning algorithms, namely BP standard algorithm, additional momentum item algorithm and learning speed self-adaptation adjustment algorithm. A plurality of nerve cell processors can be connected in series to realize pipeline algorithm, so that the self-adaptation method has the characteristics of high flexibility and high practicability and is applicable in the application field of embedded hardware BP hardware nerve networks.

Description

technical field [0001] The invention relates to the field of neural network hardware implementation, in particular to the operation of a single neuron node in a hardware BP neural network with a multi-layer structure at different operation stages and an adaptive method for realizing different learning algorithms. Background technique [0002] Artificial neural networks are widely used in intelligent control, pattern recognition and other fields, among which BP neural network is the most widely used. There are many learning algorithms of BP neural network to meet different application requirements. However, the main problem in the traditional general-purpose processor-based software implementation method is that the degree of parallelism is low, especially in the field of embedded applications, and the calculation speed cannot meet the real-time requirements of the field. The hardware implementation of neural network can meet the requirements of parallel computing, but the ha...

Claims

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Application Information

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IPC IPC(8): G05B13/04
Inventor 黄晞
Owner FUJIAN NORMAL UNIV
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