System for unified configuration and management of FPGA chip in equipment

An in-device and chip technology, which is applied in the system field of unified configuration and management of FPGA chips in the device, can solve problems such as low configuration efficiency, and achieve the effect of improving efficiency and improving configuration efficiency.
CN101485576AInactive Publication Date: 2009-07-22SHENZHEN LANDWIND IND

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHENZHEN LANDWIND IND
Publication Date
2009-07-22
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a system for unified configuration and management of FPGA chips inside equipment. The system comprises a configuration and management logic component and at least one field programmable gate array (FPGA) chip, wherein the configuration and management logic component is connected with the FPGA, and comprises a microprocessor, a nonvolatile memory and a complex programmable logic device (CPLD) which are connected with each another; the CPLD is connected with the FPGA; and the configuration and management logic component is used to realize the configuration of one or more pieces of the FPGA in a serial mode or a parallel mode. The system realizes unified configuration and management of the FPGA chips inside the equipment and greatly increases the configuration efficiency of the FPGA chips inside the equipment, thereby increasing equipment efficiency during use and maintenance.
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Description

technical field

[0001] The invention relates to the technical field of embedded systems, in particular to a system for unified configuration and management of FPGA chips in equipment. Background technique

[0002] Modern ultrasonic Doppler diagnostic instruments increasingly use FPGA (Field Programmable Gate Array, Field Programmable Gate Array), usually more than one FPGA chip. However, the FPGA chip based on the SRAM (Static RAM, static random access memory) process needs to be configured after each power-on. Usually, the configuration file of the FPGA chip is loaded by an external dedicated EPROM. This traditional configuration method is adopted when the function of the FPGA chip is relatively stable. This method is impractical and inconvenient when the system design requires high configuration speed, large capacity, maintenance and remote upgrade.

[0003] When the FPGA chip is working normally, the configuration data is stored in the SRAM unit, and this SRAM unit is a...

Claims

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