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94 results about "Subsystem design" patented technology

Guidelines: Design Subsystem. A model element which has the semantics of a package (it can contain other model elements) and a class (it has behavior). The behavior of the subsystem is provided by classes or other subsystems it contains. A subsystem realizes one or more interfaces, which define the behavior it can perform.

Time scale function decomposition based hypersonic aircraft actuator saturation control method

The invention discloses a time scale function decomposition based hypersonic aircraft actuator saturation control method. The method is used for solving the technical problem of difficulty in engineering realization under the existing hypersonic aircraft actuator saturation condition. The method includes: obtaining a high-speed slow variable subsystem, a speed slow variable subsystem and an attitude fast variable subsystem by time scale decomposition, and building a discrete form of an original system through an Eulerian method; regarding the height and the speed in a fast subsystem design process as constants so as to achieve model simplification; considering actuator saturation limitations, and importing auxiliary control variables to design throttling valve openness and the controlpiston deflexion angle; and designing an updating law of a neural network by importing an auxiliary error variable. The time scale function decomposition based hypersonic aircraft actuator saturation control method has the advantages that computer control characteristics are combined, a discrete model is built, the subsystems are designed according to time scale function decomposition, the actuator saturation condition is fully considered during controller design, and the method is suitable for engineering application.
Owner:NORTHWESTERN POLYTECHNICAL UNIV

High performance sub-system design and assembly

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input / output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input / output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.
Owner:QUALCOMM INC

High performance sub-system design and assembly

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.
Owner:QUALCOMM INC

Subsystem integration method and subsystem integration system for integration design of system-on-chip

The invention discloses a subsystem integration method for the integration design of a system-on-chip, which comprises the following steps of: 1) packaging a subsystem by adopting an IP-XACT standard, wherein the subsystem comprises a subsystem device extensible markup language (XML) file, a subsystem design XML file and a subsystem generator; 2) writing a subsystem XML file analysis tool by adopting a scripting language, analyzing instantiated devices in the subsystem, simultaneously iteratively analyzing other instantiated subsystems in the subsystem, making directories for each instantiated device, transferring working directories to the corresponding directories, calling a device generator to generate device register-transfer-level (RTL) codes and a test stimulus template, and generating a subsystem top-level code after finishing the iterative analyzing of the subsystem; 3) writing a code modifying tool by adopting the scripting language; and 4) writing a subsystem top level RTL code generation tool by adopting the scripting language. The invention also provides a subsystem integration system. The method and the system ensure high configurability, higher portability and high flexibility, and improve the integration efficiency.
Owner:C SKY MICROSYST CO LTD

Decoupling method and control device for suspension force feed-forward compensation of bearingless permanent magnet synchronous motor

The invention discloses a suspension force feedforward compensation decoupling method and a control device of a bearingless permanent magnet synchronous motor. During control, it includes an expanded current hysteresis PWM inverter configured to supply power to the torque winding of the motor; the structure is expanded The coupled levitation force model; construct an extended feedforward compensation decoupling controller; the extended feedforward compensation decoupling controller takes two levitation force components, torque current components, permanent magnet equivalent excitation current and rotational speed as its input , the reference value of the three-phase current of the suspension winding is output, and the actual three-phase current is output after the first current hysteresis PWM inverter, which is used as the input of the extended coupling suspension force model, and the extended coupling suspension force model outputs the rotor displacement; finally, the two A decoupled suspension force subsystem and speed subsystem design a closed-loop regulator. By using the invention to control the bearingless permanent magnet synchronous motor, the stable suspension of the controlled motor can be realized, and the system has fast response, simple algorithm and excellent performance.
Owner:NANJING COLLEGE OF INFORMATION TECH

Intelligent lighting management and control system realization method

The invention provides an intelligent lighting management and control system realization method and belongs to the field of Internet of things application. The system is equipped with three layers ofarchitecture comprising terminal nodes in a sensing layer, a OneNET cloud platform in a network layer, and a device service subsystem and a user service subsystem in an application layer. In the sensing layer, the terminal nodes aggregate bottom layer information to a gateway device through a Zigbee protocol and the gateway device accesses a network through an upper computer. In the network layer,the OneNET cloud platform provides an ID number for the gateway device and the gateway device is connected with the OneNET through a TCP protocol family. In the application layer, for the particularity of a node communication mode, the device service subsystem designs a DSS communication protocol and operation process in order to analyze node information aggregated to the gateway, the problems such as service object identification and uplink and downlink data correspondence are solved, a function system for communicating with sensors, carrying out control and management, storing information and supporting operation of the user service subsystem is realized, and a user can monitor the operation condition of an urban lighting system in real time.
Owner:CHONGQING UNIV OF POSTS & TELECOMM

High performance sub-system design and assembly

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.
Owner:QUALCOMM INC

Super-size flexible spacecraft dispersion cooperative control method

The invention discloses a super-size flexible spacecraft dispersion cooperative control method, and aims to achieve high stability and vibration inhibition control on a super-size flexible spacecraft. The method comprises the following steps: S1, dividing a super-size flexible spacecraft control system into a spacecraft posture control subsystem and a flexible attachment vibration subsystem, and designing corresponding partial robust controllers for the spacecraft posture control subsystem and the flexible attachment vibration subsystem respectively; and S2, designing a coordinate controller for overall properties of the super-size flexible spacecraft control system. The method has the advantages that according to the dynamic characteristics of the super-size flexible spacecraft, a dispersion cooperative control method is adopted, a partial structure is stably controlled through dispersion stability, overall high-precision performance indexes are achieved through the cooperative controller, high appointing precision and stability of postures and deformation control precision of a flexible component are achieved, and the method is widely applied to high-precision high-stability appointing control on a large-size flexible structure.
Owner:SHANGHAI AEROSPACE CONTROL TECH INST
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