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Subsystem integration method and subsystem integration system for integration design of system-on-chip

A system-on-a-chip, integration method technology, applied in computing, special data processing applications, instruments, etc., can solve the problems of low integration efficiency, low flexibility, and low subsystem integration configurability

Active Publication Date: 2011-04-13
C SKY MICROSYST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to overcome the shortcomings of low configurability, poor portability, low flexibility, and low integration efficiency of subsystem integration in existing system chip designs, the present invention provides a high configurability, good portability, high flexibility, and improved integration Efficient Subsystem Integration Method for System-on-Chip Integration Design and Subsystem Integration System

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  • Subsystem integration method and subsystem integration system for integration design of system-on-chip
  • Subsystem integration method and subsystem integration system for integration design of system-on-chip
  • Subsystem integration method and subsystem integration system for integration design of system-on-chip

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Embodiment 1

[0070] refer to Figure 1 to Figure 6 , a subsystem integration method for system chip integration design, the subsystem integration method comprises the steps of:

[0071] 1) Adopt the IP-XACT standard to package the subsystem, and the subsystem includes the XML file of the subsystem device, the XML file of the subsystem design and the subsystem generator;

[0072] 2) Write a subsystem XML file analysis tool using script language. During the instantiation process of the subsystem, analyze the instantiated devices in the subsystem, and analyze other subsystems instantiated in the subsystem iteratively at the same time, for each instantiation Create a directory for the device, and transfer the working directory to the corresponding directory, call the device generator to generate the device RTL code and test stimulus template, and use the code modification tool in step 3) to modify the module and macro name; when the iterative analysis of the subsystem is completed After that,...

example

[0111] Example: The IP owned by Hangzhou Zhongtian Microsystems is packaged into a library using the IP-XACT standard. The IP of Hangzhou Zhongtian Microsystems is composed of two parts: one is the IP independently developed by the company, including CKCore embedded with independent intellectual property rights type processor, h.264 video decoder, etc.; the second is DesignWare IP based on Synoposis. Based on the SoC architecture of Hangzhou Zhongtian Microsystems, commonly used functional modules are packaged into subsystems, mainly including: video subsystem, audio subsystem, peripheral interface subsystem, etc. Put all packaged IP and subsystems into the IP library, and the IP library is named aphrodite.

[0112] Write the subsystem design XML file analysis tool in Perl language and name it design_parser to extract relevant information from the subsystem XML file and pass it to the subsystem top-level RTL code generation tool through the internal data structure of Perl to g...

Embodiment 2

[0155] refer to Figure 1 to Figure 6 , a subsystem integration system for system chip integration design, the subsystem integration system includes: subsystem device XML file, used to describe the VLNV information of the subsystem, bus interface, physical port, configuration parameters, subsystem generation In the system chip integration process, the subsystem is integrated as a common IP and indexed from the IP library through VLNV information;

[0156] The subsystem design XML file is used to describe the instantiated IP in the subsystem and the interconnection between IPs;

[0157] The subsystem generator is used to modify the components and design XML files of the subsystem according to the configuration parameters;

[0158] The subsystem design XML file analysis tool is used to extract the information of each part step by step from the subsystem XML file and save it in the internal data structure of the script, and then call the subsystem top-level RTL code gen...

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Abstract

The invention discloses a subsystem integration method for the integration design of a system-on-chip, which comprises the following steps of: 1) packaging a subsystem by adopting an IP-XACT standard, wherein the subsystem comprises a subsystem device extensible markup language (XML) file, a subsystem design XML file and a subsystem generator; 2) writing a subsystem XML file analysis tool by adopting a scripting language, analyzing instantiated devices in the subsystem, simultaneously iteratively analyzing other instantiated subsystems in the subsystem, making directories for each instantiated device, transferring working directories to the corresponding directories, calling a device generator to generate device register-transfer-level (RTL) codes and a test stimulus template, and generating a subsystem top-level code after finishing the iterative analyzing of the subsystem; 3) writing a code modifying tool by adopting the scripting language; and 4) writing a subsystem top level RTL code generation tool by adopting the scripting language. The invention also provides a subsystem integration system. The method and the system ensure high configurability, higher portability and high flexibility, and improve the integration efficiency.

Description

technical field [0001] The invention relates to the field of system chip (SoC) integration design, in particular to a method for automatically implementing repeated iterations of subsystems in the subsystem integration process, and a subsystem integration system. Background technique [0002] With the continuous improvement of the manufacturing level of integrated circuits, designers can integrate complex systems with millions of gates on a single chip, that is, System-On-Chip. In recent years, SoC has become the mainstream direction of todays integrated circuit design. With the continuous improvement of embedded product performance requirements, the complexity of SoC design is also increasing. At present, SoC designers are mainly faced with two challenges: on the one hand, the improvement of SoC integration makes SoC design more complicated, which brings great difficulty in verification; on the other hand, embedded products are updated more frequently, and the TTM of SoC pr...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 葛海通李春澍黄凯严晓浪
Owner C SKY MICROSYST CO LTD
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