Parallel multi-core FPGA digital image real-time zooming processing method and device

A digital image and processing method technology, which is applied in the field of parallel multi-core FPGA digital image real-time scaling processing and devices, can solve the problem of high system cost, and achieve the effect of taking into account processing efficiency, reducing calculation clock frequency, and reducing complexity

Inactive Publication Date: 2014-10-15
DALIAN NATIONALITIES UNIVERSITY
View PDF3 Cites 62 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] For this reason, the object of the present invention is to propose a kind of parallel multi-core FPGA digital image that simplifies the system structure and can be realized without sync...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Parallel multi-core FPGA digital image real-time zooming processing method and device
  • Parallel multi-core FPGA digital image real-time zooming processing method and device
  • Parallel multi-core FPGA digital image real-time zooming processing method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] With the development of technology, the demand for video display technology is no longer solely limited to how to display higher-resolution video information on a larger screen, but also how to enlarge low-resolution video information to the corresponding display in real time. The screen size is displayed on the high resolution screen. It is not difficult to see from this that the development of video display technology is no longer limited only by the display technology itself, but in some applications is more limited by the quality, real-time, processing method and processing chip operation of the required video information. ability.

[0044] Based on this, this embodiment provides a high-efficiency parallel digital video image real-time scaling processing method to balance the contradiction between the system processing capacity and the higher requirements for throughput and real-time performance of digital video image scaling, thereby reducing System cost and the purp...

Embodiment 2

[0062] In this embodiment, when selecting the required number of scaling cores, select the smallest number of scaling cores, and input the pixel clock frequency CLK in , Output pixel clock frequency CLK out , After comparing, get the highest frequency of the pixel clock CLK=max{CLK in , CLK out }, the upper limit working clock frequency of a single scaling core is CLK Smax , Then the number of scaling cores n is a positive integer, then when CLK / CLK Smax When it is an integer, n=CLK / CLK Smax ; When CLK / CLK Smax When it is a non-integer, n=[CLK / CLK Smax ]+1, [·] means rounding operation.

[0063] In addition, in this embodiment, the method of longitudinal uniform division is adopted when dividing the original video image data. Since the monitor works in a raster scan (raster scan) mode, the pixels are output in order from the top left to the bottom right. In this embodiment, the video image is uniformly divided longitudinally according to the characteristics of the r...

Embodiment 3

[0066] A device using the parallel multi-core FPGA digital image real-time scaling processing method described in embodiment 1 or 2, comprising

[0067] Input module: Use the SiI1161 chip of Silicon Image to obtain the original video image data to be processed, and input the original video image data into the Spartan-6XC6SLX100 FPGA chip produced by Xilinx;

[0068] Scaling core calculation module: Determine the number of scaling cores according to the input pixel clock frequency, output pixel clock frequency and the upper limit working clock frequency of a single scaling core;

[0069] Segmentation module: segment the original video image data according to the number of zoom cores and obtain each segmented image sub-block;

[0070] Storage module: Store the divided image data in the external DDR buffer, the model is Micron MT47H32M16-25;

[0071] Scaling module: Return the data in the buffer to the FPGA chip for processing. Each image sub-block after segmentation undergoes a scaling co...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

Provided is a parallel multi-core FPGA digital image real-time zooming processing method and device. The method comprises the steps that original video image data to be processed are acquired firstly. The original video image data are inputted to an FPGA chip and the number of zooming cores is confirmed, and the original video image data are divided into image sub-blocks having the same number with that of the zooming cores. Then the divided data are stored in a buffer, the data in the buffer are returned to the FPGA and parallel zooming processing is performed on each image sub-block via one zooming core respectively so that zooming is completed. All the image sub-blocks after zooming are displayed after splicing processing. The method has certain guiding effect on high throughput and high real-time application of digital video images.

Description

Technical field [0001] The invention relates to a method and device for processing image enlargement or reduction, in particular to a method and device for processing parallel multi-core FPGA digital images in real time. Background technique [0002] The rapid development of electronic products and electronic technology has driven the continuous improvement of display technology. With the continuous development of video display technology and display terminal manufacturing technology, the resolution required by various video applications and the size of display terminals are constantly increasing. Not only have 1920×1080 and higher resolutions appeared, but also display terminal The size is constantly breaking through the limits of the manufacturing process, especially the emergence of screen splicing technology and projection fusion technology has further improved the display resolution and size of the display terminal. At the same time, applications such as modern media promot...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H04N5/262G06T1/20
Inventor 杨大伟张汝波刘冠群毛琳吴俊伟
Owner DALIAN NATIONALITIES UNIVERSITY
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap