Multiple chips automatic test method based on programmable logic device

A technology of programming logic and automatic testing, which is applied in digital circuit testing, electronic circuit testing, etc., can solve problems such as long debugging cycle, high cost, and complicated testing process, and achieve fast development speed, low investment cost, and satisfy small batch products The effect of the test

Inactive Publication Date: 2008-04-09
无锡汉柏信息技术有限公司
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Problems solved by technology

But its cost is high, the testing process is complicated, and the debugging cycle is long

Method used

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  • Multiple chips automatic test method based on programmable logic device
  • Multiple chips automatic test method based on programmable logic device

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Embodiment Construction

[0012] As shown in the figure: the programmable logic device includes a sampling circuit connected to each other, a digital comparator circuit, a decoder and an excitation generating circuit, and its characteristics are: the input terminal of the digital comparator circuit and the output terminal of the multiplexer Connection, the input terminal of the sampling circuit is connected with several chips under test; the multiplexer provides digital input signals for the digital comparator circuit; the chip under test provides digital input signals after analog-to-digital conversion for the sampling circuit; It is connected with several tested chips and one tested chip, and provides input signals and clock signals for the tested chip and the tested chip; the output terminal of the decoding circuit is connected with the multiplexer, and provides the loop control signal for the multiplexer , so that the multiplexer selects the output signal of the chip under test to be tested.

[001...

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Abstract

The invention relates to an automatic testing technology for molectron, in particular to an automatic testing method for multiple chips based on field programmable gate array (FPGA). According to the technical scheme provided by the invention, the field programmable gate array comprises the sample circuits that are connected to each other, a circuit of digital comparator, an encoder, and a pulse generating circuit. The technical scheme is characterized in that the input end of the circuit of digital comparator is connected with the output end of a multiplexer, the input end of the sample circuit is connected with a plurality of chips being tested; and the pulse generating circuit is connected with a plurality of chips being tested and a tested chip respectively; the output end of the encoder circuit is connected with the multiplexer. The invention uses the field programmable gate array (FPGA) to set up a simple automatic testing system, in which the automatic testing of a single or a plurality of chips can be implemented simultaneously on a testing board, The invention achieves automatic testing and has low input cost and rapid development, thus completely satisfying the requirement for the testing of small-lot products.

Description

technical field [0001] The invention relates to integrated circuit automatic testing technology, in particular to a multi-chip automatic testing method based on a programmable logic device (FPGA). Background technique [0002] Integrated circuit testing is an important part of chip development. At present, integrated circuit testing includes manual testing and automated testing. Automated testing is fast, high-level, and comprehensive, so it is widely used in mass product testing. But its cost is high, the testing process is complicated, and the debugging cycle is long. The manual test is generally implemented on a customized test board, and is completed by the tester observing the light, sound or instrument reading. Manual testing is suitable for small batch, simple, non-comprehensive quick testing. Contents of the invention [0003] The purpose of the present invention is to design a kind of multi-chip automatic test method based on programmable logic device, combine...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317
Inventor 唐伟
Owner 无锡汉柏信息技术有限公司
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