23 results about "Digital comparator" patented technology

A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.

The invention discloses a magnetic axis keyboard Hall sensor array reading circuit and a reading method. The device comprises a Hall sensor array, a controllable power supply array, a control module, two 1-out-of-N selectors, an analog comparator, a digital comparator, an analog-to-digital converter and a digital-to-analog converter. The power supply end of each Hall sensor is connected with the output end of the corresponding controllable power supply, and signals input by the high-voltage enabling end and the low-voltage enabling end of each controllable power supply are not high levels at the same time. A mobile threshold register and a trigger threshold register are arranged in the control module, output ends of the N Hall sensors are respectively connected with corresponding input ends of the two one-out-of-N selectors, and the two one-out-of-N selectors are respectively connected with the mobile threshold register and the trigger threshold register through the analog comparator and the digital comparator. According to the invention, adaptive frequency modulation and voltage regulation can be carried out, the working current of the Hall sensor array is greatly reduced, the working time of the magnetic axis keyboard is prolonged, and the key delay is reduced.

The invention relates to the technical field of electronics, and discloses a VOT compensation-based single-phase interleaved CRM PFC digital control system and method, and the system comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator, and a driver. An EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module are integrated in the DSP controller, a 2P2Z controller, a voltage feedforward operation unit, a current detection verification unit and a temperature protection unit are further arranged in the DSP controller, the TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is provided with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase and two-phase staggered Boost topology, and the two Boost circuits are staggered and connected in parallel at a 180-degree initial phase and are jointly connected to the same PFC bus. According to the invention, the circuit design is simplified, the dynamic stability of inductive current interleaving is optimized, and the THD index of the power supply is improved.

The invention provides an adjustable probability random number generator based on an MRAM (Magnetic Random Access Memory) and electronic equipment. The random number generator comprises an MTJ random number generation unit which is used for adopting an MTJ device as an entropy source to output an original random bit stream, and the 0 / 1 distribution probability of each bit is 50%; the shift register module is used for continuously receiving the original random bit stream for N times and generating an N-bit binary accumulated value, and N is an integer greater than or equal to 2; the threshold register module is used for storing a preset threshold T, and T is an integer between 0 and 2N-1; and the digital comparator module is used for comparing the N-bit binary accumulated value with a preset threshold value T, outputting a first logic value when the N-bit binary accumulated value is greater than or equal to T, and otherwise, outputting a second logic value. Therefore, the probability distribution of the binary bit stream output by the random number generator can be dynamically adjusted through a digital threshold segmentation method, an additional simulation regulation and control circuit does not need to be modified and introduced, and the method is suitable for cryptography, Monte Carlo simulation and a self-adaptive probability calculation system.

The invention relates to the field of motor driving, in particular to a direct current motor parameter on-line measuring system which comprises a digital control unit, an H bridge, a first analog comparator, a second analog comparator, a first analog-to-digital converter and a second analog-to-digital converter. The first analog comparator and the second analog comparator compare the tail current with a preset current value given by the digital control unit, the comparison result is sent to the digital control unit, the digital control unit carries out calculation processing on the comparison result, accurate detection of the inductance, the resistance, the rotating speed, the average current I and the current ripple of the motor is achieved, the system does not need an additional sensor, and the cost is reduced. Only two comparators are needed, so that the system cost and the installation complexity are greatly reduced; inductance and resistance can be measured at the initial starting stage; and motor current (ripple and average current) and rotating speed conditions are monitored in real time.

The application discloses a random number conversion system based on a self-calibration magnetic tunnel junction and a working method thereof, and the system comprises a magnetic tunnel junction, a magnetic tunnel junction random writing module, a pre-charge sensing amplification module and a real-time feedback calibration module; the magnetic tunnel junction is a source of physical randomness of the system, and the resistance state of the magnetic tunnel junction randomly flips based on thermal fluctuation; the output end of the magnetic tunnel junction random writing module is connected with the magnetic tunnel junction; the input end of the pre-charge sensing amplification module is connected with the magnetic tunnel junction; the real-time feedback calibration module comprises a period counter, a flip counter and a digital comparator; the input end of the flip counter is connected with the output end of the pre-charge sensing amplification module; the output end of the digital comparator is connected with the input end of the magnetic tunnel junction random writing module, and the flip current of the magnetic tunnel junction random writing module is dynamically adjusted. The application solves the problem of flip probability deviation of a traditional true random number generator caused by process deviation and environmental temperature fluctuation.

An amplifier (11) performs analog amplification on a signal (I_A) with a gain corresponding to a state (GS) and outputs it as a signal (M_A). An ADC (12) converts the signal (M_A) into a digital signal and outputs it as a signal (M_D). Analog comparators (13 and 14) and a decrement determination unit (24) detect that the signal (M_A) exceeds a first level and cause the state (GS) to transition to a state with a gain one level lower. Digital comparators (21 and 22) and an increment determination unit (23) detect that the signal (M_D) continuously falls below a second level during a specified period and cause the state (GS) to transition to a state with a gain one level higher. A restoration circuit (27) performs digital amplification on the signal (M_D) with a gain corresponding to the gain of the amplifier (11) and outputs it as a signal (O_D).

The invention relates to an Automatic test equipment (ATE) (2) for testing a device under test (DUT)(20), comprising: a test pin (4), a digital comparator (6), and a source (8) for encoded data, wherein the ATE (2) is configured to communicate with the DUT (20) through the test pin (4). The invention further relates to a method for automatic testing of a DUT device and to a system comprising the ATE and the DUT.

The fingerprint recognition device of the present invention comprises: a substrate; a sensor located on the substrate and surrounded by a plurality of sensing finger touch pads; an oscillator electrically connected to the plurality of sensing finger touch pads and outputting at least one oscillation frequency signal; a timer outputting a clock signal to the oscillator; and a counting and digital comparator counting and comparing the oscillation frequency signal. The fingerprint recognition method of the present invention comprises: the oscillator receiving the clock signal and outputting the oscillation frequency signal; a finger touching the plurality of sensing finger touch pads; and counting and comparing the oscillation frequency signal and the oscillation frequency signal after touching. The present invention is applied to the display surface of an electronic product and senses whether a finger touches the fingerprint recognition device.

The invention relates to a communication apparatus and a control method for reducing power consumption. The communication device comprises a crystal oscillator, an auxiliary circuit and a control circuit. The crystal oscillator can provide a clock in a second mode for operation of the communication device. The auxiliary circuit comprises an accumulator and a comparator. The accumulator can calculate a number according to a medium-dependent interface signal. The comparator can compare the number with a critical value. If the number is greater than or equal to the critical value, the comparator can output a wake-up signal. The control circuit can respond to a control signal to switch from the second mode to a first mode, and can respond to the wake-up signal to switch from the first mode to the second mode. In the first mode, the control circuit can disable the crystal oscillator and can enable the auxiliary circuit. In the second mode, the control circuit can enable the crystal oscillator.

In a digital envelope detector circuit, an input terminal receives a digital input signal and an output terminal produces a digital output signal. First and second digital processing circuitry between the input and output terminals each includes a memory element. The first processing circuitry applies low-pass filtering to the digital input signal. The second processing circuitry processes the digital input signal, stores in the memory element a value indicative of the processed digital input signal, and processes the output from the memory element so that the digital input signal is passed unaltered. A digital comparator circuit compares the digital input and output signals, asserts a control signal in response to the digital input signal being higher, and de-asserts the control signal in response to the digital input signal being lower. The first / second processing circuitry produces the digital output signal in response to the control signal being de-asserted / asserted.

The present invention discloses a low-power tag detection circuit for RFID, including: a transmitting circuit, a receiving filter circuit, an 8-bit AD circuit and a tag detection logic circuit, wherein: the transmitting circuit includes an internal clock circuit and two driving circuits; under the control of the tag detection logic circuit, when the tag needs to be detected, the internal clock circuit is enabled to generate a 13.56MHz clock; the receiving filter circuit is composed of a sampling follower circuit and an active filter circuit, and two differential inputs are connected by an external coil to the sampling follower circuit; the 8-bit AD circuit is composed of a comparator, an 8-bit DA module and an AD control unit; the tag detection logic circuit includes two modules, a timer and a digital comparator. By setting the counting time of the timer, the entire tag detection system is started at a fixed time, and an enabling control signal of the transmitting circuit, the receiving filter circuit and the 8-bit AD circuit is generated. The present invention determines whether to start the RFID radio frequency identification system by judging whether there is a tag card receiving energy, thereby reducing unnecessary startups and achieving the effect of reducing power consumption.

An active shielding device comprising a current source; an analog line shield unit; a switch; a current-to-voltage converter configured to generate a voltage in response to a current generated by the current source and a digital control sequence for the switch; a voltage comparator configured to compare the voltage generated by the current-to-voltage converter to a reference voltage; a digital active shield unit; digital logic configured to process the digital control sequence before and after conducting the digital control sequence through the digital active shield unit to generate a first processed result signal and a second result signal; and a digital comparator configured to compare the first processed result signal to the second result signal.

The invention relates to a transceiver device (12; 120; 1200) for a subscriber station (10; 30) of a serial bus system (1) and to a method for transmitting differential signals (CAN_H, CAN_L; VDIFF) in a serial bus system (1). The transceiver device (12; 120; 1200) has: a first comparator (151) for evaluating differential signals (CAN_H, CAN_L; VDIFF) received from a bus (40) of the bus system (1), with a first reception threshold (T1), in order to generate a first digital comparator output signal (CA1); a second comparator (152) for evaluating the differential signals (CAN H, CAN L; VDIFF) received from the bus (40), with a second reception threshold (T2) different from the first reception threshold (T1), in order to generate a second digital comparator output signal (CA2); a logic circuit (1222) for combining the first and second digital comparator output signals (CA1, CA2) in order to output a reception signal (RxD; RxD1; RxD2) to a communication control device (11) of the subscriber station (10; 30); and a filter block (154; 154A; 154B) for evaluating the reception signal (RxD) and the second comparator output signal (CA2) in order to decide whether or not the second digital comparator output signal (CA2) should, with a delay, be output to the logic circuit (1222), and for outputting the second digital comparator output signal (CA2) to the logic circuit (1222) on the basis of the evaluation by the filter block (154; 154A; 154B).

The invention discloses a dynamic electrocardiogram signal simulation generator, which can output an electrocardiogram signal as low as 1uV-10uV according to its true voltage value, thereby ensuring the accuracy of dynamic electrocardiogram performance detection. The generator includes a touch display screen, a data update interface, a Flash memory, a processor, a digital-to-analog converter, a digital comparator, a signal amplitude adjustment circuit and a 3.5mm coaxial analog signal output interface; the processor is connected to the touch display screen for user operation; the processor is connected to the Flash memory for storing electrocardiogram signals; the processor is connected to the digital-to-analog converter for converting the electrocardiogram signal from a digital quantity to an analog quantity; the processor is connected to the digital comparator; the data comparator determines whether the electrocardiogram signal to be output is less than a set threshold value, and then outputs the comparison result to the signal amplitude adjustment circuit; the digital-to-analog converter is electrically connected to the 3.5mm coaxial analog signal output interface through the signal amplitude adjustment circuit.

The invention relates to the technical field of circuit control, and discloses an LED analog dimming control circuit. The invention obtains the relevant count of an input square wave signal through a cycle counter module and a high level counter module, and then performs cyclic comparison and subtraction operations through a digital comparator module and a subtractor module until the subtraction result is less than a judgment threshold extracted from the square wave signal, thereby completing a comparison cycle and entering the next comparison cycle. The number of subtraction operations in each working cycle is converted into an analog signal through a DAC module to adjust the LED current, thereby solving the problem that the analog dimming control circuit in the prior art cannot take into account both response speed and cost control.

The application relates to the field of electronic technology and discloses a single-phase interleaved CRM PFC digital control system and method based on VOT compensation, which comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator and a driver. The DSP controller is internally integrated with an EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module, and is further internally provided with a 2P2Z controller, a voltage feed-forward operation unit, a current detection checking unit and a temperature protection unit. The TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is configured with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase two-phase interleaved Boost topology, two Boost circuits are connected in parallel with an initial phase difference of 180 degrees, and are commonly connected to the same PFC bus. The application simplifies the circuit design, optimizes the dynamic stability of inductance current interleaving and improves the power THD index.

The present disclosure relates to systems and methods that provide an accurate angle measurement of a rotatable mirror. An example method includes causing a light-emitter device to emit emission light along an optical axis toward a rotatable mirror, such that the emission light interacts with a reflective surface of the rotatable mirror to provide reflected light. The rotatable mirror is configured to rotate about a rotational axis. The method also includes receiving, from a detector device, a reflected light signal. The method also includes determining, by a detector readout circuit and based on the reflected light signal, a rotational angle of the rotatable mirror. Determining the rotational angle of the rotatable mirror involves providing, by a digital comparator, a digital signal comprising information indicative of rising and falling edges of an analog signal based on a current pulse from the detector device.

A sensor device for light sensing for light-to-frequency conversion. The sensor device includes a photodiode, an analog-to-digital converter (ADC) operable to perform a clipping technique in response to a first clock signal (CLK1) and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing a digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of clipping switches coupled to a first amplifier, a second set of clipping switches electrically coupled to the output of the first amplifier and electrically coupled to an input terminal of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.

The present invention discloses a signal gain value judgment circuit and related methods. The signal gain value judgment circuit includes a digital comparator, a digital controller, and an arithmetic module. A first buffer is used to store a predetermined count value. A sensing integration circuit generates a first count value based on a first sensing signal within a first integration time. The digital comparator is used to compare the first count value with the predetermined count value to generate a comparison result. The digital controller is used to generate a control signal indicating a signal gain value based on the comparison result to provide to a signal amplifier of the sensing integration circuit; wherein the signal amplifier adjusts the first sensing signal based on the signal gain value to generate a second sensing signal, so that the sensing integration circuit generates a second count value corresponding to the second sensing signal within a second integration time. The arithmetic module is used to generate an output count value corresponding to the first sensing signal based on the second count value and the signal gain value.

A method and apparatus (4) for eliminating an output jitter of a sensor, and a sensor (1). The method comprises: acquiring a current digital temperature signal and a digital temperature signal stored at a previous time at an interval of a preset time (S1); comparing the current digital temperature signal with the digital temperature signal stored at the previous time at an interval of a preset time to obtain a digital temperature signal variation (S2); and determining whether the digital temperature signal variation is greater than a preset threshold, and when the digital temperature signal variation is greater than the preset threshold, updating and outputting the current digital temperature signal (S3). The apparatus (4) comprises a register (11), an absolute value operator (12), and a digital comparator (13). The sensor (1) comprises a main sensor (2), a temperature calibration circuit (3), and the apparatus (4). Without increasing the resolution of an ADC, the output jitter of the sensor (1) is effectively eliminated, and costs are reduced.