8 results about "Digital comparator" patented technology

The invention discloses a magnetic axis keyboard Hall sensor array reading circuit and a reading method. The device comprises a Hall sensor array, a controllable power supply array, a control module, two 1-out-of-N selectors, an analog comparator, a digital comparator, an analog-to-digital converter and a digital-to-analog converter. The power supply end of each Hall sensor is connected with the output end of the corresponding controllable power supply, and signals input by the high-voltage enabling end and the low-voltage enabling end of each controllable power supply are not high levels at the same time. A mobile threshold register and a trigger threshold register are arranged in the control module, output ends of the N Hall sensors are respectively connected with corresponding input ends of the two one-out-of-N selectors, and the two one-out-of-N selectors are respectively connected with the mobile threshold register and the trigger threshold register through the analog comparator and the digital comparator. According to the invention, adaptive frequency modulation and voltage regulation can be carried out, the working current of the Hall sensor array is greatly reduced, the working time of the magnetic axis keyboard is prolonged, and the key delay is reduced.

The invention relates to the technical field of electronics, and discloses a VOT compensation-based single-phase interleaved CRM PFC digital control system and method, and the system comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator, and a driver. An EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module are integrated in the DSP controller, a 2P2Z controller, a voltage feedforward operation unit, a current detection verification unit and a temperature protection unit are further arranged in the DSP controller, the TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is provided with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase and two-phase staggered Boost topology, and the two Boost circuits are staggered and connected in parallel at a 180-degree initial phase and are jointly connected to the same PFC bus. According to the invention, the circuit design is simplified, the dynamic stability of inductive current interleaving is optimized, and the THD index of the power supply is improved.

The invention provides an adjustable probability random number generator based on an MRAM (Magnetic Random Access Memory) and electronic equipment. The random number generator comprises an MTJ random number generation unit which is used for adopting an MTJ device as an entropy source to output an original random bit stream, and the 0 / 1 distribution probability of each bit is 50%; the shift register module is used for continuously receiving the original random bit stream for N times and generating an N-bit binary accumulated value, and N is an integer greater than or equal to 2; the threshold register module is used for storing a preset threshold T, and T is an integer between 0 and 2N-1; and the digital comparator module is used for comparing the N-bit binary accumulated value with a preset threshold value T, outputting a first logic value when the N-bit binary accumulated value is greater than or equal to T, and otherwise, outputting a second logic value. Therefore, the probability distribution of the binary bit stream output by the random number generator can be dynamically adjusted through a digital threshold segmentation method, an additional simulation regulation and control circuit does not need to be modified and introduced, and the method is suitable for cryptography, Monte Carlo simulation and a self-adaptive probability calculation system.

The application discloses a random number conversion system based on a self-calibration magnetic tunnel junction and a working method thereof, and the system comprises a magnetic tunnel junction, a magnetic tunnel junction random writing module, a pre-charge sensing amplification module and a real-time feedback calibration module; the magnetic tunnel junction is a source of physical randomness of the system, and the resistance state of the magnetic tunnel junction randomly flips based on thermal fluctuation; the output end of the magnetic tunnel junction random writing module is connected with the magnetic tunnel junction; the input end of the pre-charge sensing amplification module is connected with the magnetic tunnel junction; the real-time feedback calibration module comprises a period counter, a flip counter and a digital comparator; the input end of the flip counter is connected with the output end of the pre-charge sensing amplification module; the output end of the digital comparator is connected with the input end of the magnetic tunnel junction random writing module, and the flip current of the magnetic tunnel junction random writing module is dynamically adjusted. The application solves the problem of flip probability deviation of a traditional true random number generator caused by process deviation and environmental temperature fluctuation.

The invention relates to an Automatic test equipment (ATE) (2) for testing a device under test (DUT)(20), comprising: a test pin (4), a digital comparator (6), and a source (8) for encoded data, wherein the ATE (2) is configured to communicate with the DUT (20) through the test pin (4). The invention further relates to a method for automatic testing of a DUT device and to a system comprising the ATE and the DUT.

In a digital envelope detector circuit, an input terminal receives a digital input signal and an output terminal produces a digital output signal. First and second digital processing circuitry between the input and output terminals each includes a memory element. The first processing circuitry applies low-pass filtering to the digital input signal. The second processing circuitry processes the digital input signal, stores in the memory element a value indicative of the processed digital input signal, and processes the output from the memory element so that the digital input signal is passed unaltered. A digital comparator circuit compares the digital input and output signals, asserts a control signal in response to the digital input signal being higher, and de-asserts the control signal in response to the digital input signal being lower. The first / second processing circuitry produces the digital output signal in response to the control signal being de-asserted / asserted.

The application relates to the field of electronic technology and discloses a single-phase interleaved CRM PFC digital control system and method based on VOT compensation, which comprises a DSP controller, a first power loop, a second power loop, a first off-chip comparator, a second off-chip comparator and a driver. The DSP controller is internally integrated with an EPWM driving module, an ADC sampling module, an on-chip DC digital comparator module and a TZ trigger interrupt module, and is further internally provided with a 2P2Z controller, a voltage feed-forward operation unit, a current detection checking unit and a temperature protection unit. The TZ trigger interrupt module is provided with a TZ2 pin and a TZ3 pin, and the EPWM driving module is configured with a first comparison register CMPA, a period register TBPRD and a second comparison register CMPB. The first power loop and the second power loop form a single-phase two-phase interleaved Boost topology, two Boost circuits are connected in parallel with an initial phase difference of 180 degrees, and are commonly connected to the same PFC bus. The application simplifies the circuit design, optimizes the dynamic stability of inductance current interleaving and improves the power THD index.