Phase-locked loop with correction and correction method thereof

Abstract

The invention provides a phase-locked loop with correction and a correction method thereof, which are used for reducing jitter of an output clock of the phase-locked loop. The phase-locked loop with correction is divided into a main loop and a correction loop, wherein the main loop comprises a frequency discriminator / phase discriminator, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider; the correction loop comprises a lock detector, a time digital converter, two counters, two digital comparators and a digital to analog converter, and the specific connection mode is that a feedback clock and a reference clock are taken as input of the time lock detector and input of the time digital converter; the output of the time digital converter is connected to the input of the first counter and the input of the second counter; the output of the first counter and the output of the second counter are respectively connected to the input of the first comparator and the input of the second comparator, and the outputs of the comparators and the output of the lock detector are connected to the input of the digital to analog converter; the output of the digital to analog converter is connected to the charge pump for controlling the output current of the charge pump.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, relates to a phase-locked loop in the microelectronic technology, in particular to a phase-locked loop with correction and a correction method thereof. Background technique [0002] As the performance of integrated circuits continues to improve, the main frequency of microprocessors is also gradually increasing. Inside the chip, a stable high-frequency clock generation circuit is particularly important. However, due to the interference of noise, the impact of clock offset and jitter on system performance is very obvious, and it is difficult to obtain a high-speed and stable clock with a simple oscillator. Today, in the field of integrated circuits, phase-locking technology is widely used to generate high-speed and high-precision clock signals. [0003] The usual phase-locked loop structure is as figure 1 As shown, it consists of a frequency / phase detector (PFD), a charge pump (CP), a ...

AI Technical Summary

Problems solved by technology

However, due to noise interference, the impact of clock offset and jitter on system performance is very obvious, and it is difficult to obtain a high-speed and stable clock with a simple oscillator.

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