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Pseudo digital low-pressure-difference linear voltage stabilizer and power management chip

A low dropout linear and voltage regulator technology, applied in the field of electronics, can solve problems such as poor transient response performance, and achieve the effect of ensuring low dropout, improving transient performance, and avoiding glitches

Active Publication Date: 2018-09-07
SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing low-dropout linear regulators have poor transient response performance.

Method used

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  • Pseudo digital low-pressure-difference linear voltage stabilizer and power management chip
  • Pseudo digital low-pressure-difference linear voltage stabilizer and power management chip
  • Pseudo digital low-pressure-difference linear voltage stabilizer and power management chip

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Embodiment Construction

[0054] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

[0055] figure 1 A circuit diagram of a pseudo-digital low-dropout linear regulator provided for an embodiment of the present invention. see figure 1 , the pseudo-digital low-dropout linear regulator consists of: NMOS transistor M P , a digital comparator 10 , a charge pump 20 and a gate level regulator 30 .

[0056] NMOS transistor M P The drain of the power supply voltage signal line VDD is electrically connected, and the NMOS transistor M P The source of the pseudo-digital low-dropout linear regulator is co...

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PUM

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Abstract

The invention discloses a pseudo digital low-pressure-difference linear voltage stabilizer and a power management chip. The pseudo digital low-pressure-difference linear voltage stabilizer comprises an NMOS transistor, a digital comparator, a charge pump and a grid level adjuster. A first input end of the digital comparator is electrically connected with an output end of the pseudo digital low-pressure-difference linear voltage stabilizer. A second input end of the digital comparator is electrically connected with a reference voltage signal line. A first gating end of the charge pump is electrically connected with an output end of the digital comparator. A power input end of the charge pump is electrically connected with a power voltage signal line. An input end of the grid level adjusteris electrically connected with an output end of the charge pump. A control end of the grid level adjuster is electrically connected with an output end of the digital comparator. An output end of the grid level adjuster is electrically connected with a grid of the NMOS transistor. The transient response performance and the working performance under low power voltages of the pseudo digital low-pressure-difference linear voltage stabilizer are improved, the circuit structure is simplified, and the chip area is reduced.

Description

technical field [0001] The embodiment of the present invention relates to electronic technology, in particular to a pseudo-digital low-dropout linear regulator and a power management chip. Background technique [0002] As users have higher and higher requirements for portable electronic products, power management chips are developing in the direction of low power supply voltage, low power consumption and fast transient response. [0003] Low-dropout linear regulators have stable output voltage and small voltage ripple, and play a vital role in power management chips. However, the existing low dropout linear regulator has the problem of poor transient response performance. Contents of the invention [0004] The invention provides a pseudo-digital low-dropout linear voltage regulator and a power management chip to improve the transient response performance of the low-dropout linear voltage regulator. [0005] In the first aspect, an embodiment of the present invention prov...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/567
CPCG05F1/567
Inventor 詹陈长汤俊尧
Owner SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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