13 results about "NvSRAM" patented technology

A non-volatile static random-access memory (NVSRAM) device includes at least one array of NVSRAM cells. Each NVSRAM cell includes an SRAM unit and an MRAM unit. The SRAM unit includes at least six transistors, and the MRAM unit includes at least two-transistors and two magnetic tunnel junction (MTJ) structures. The SRAM units are accessed during normal read / write operations to allows for fast access to the NVSRAM cells with unlimited endurance and without read / write error rate issues. Hidden MRAM write operations in NVSRAM cells that are not accessed for normal read / write operations may be activated manually or automatically to back up the data stored in the corresponding SRAM units. When the NVSRAM device loses power, data stored in the SRAM units are lost, while the data backed-up in corresponding MRAM units are retained. When power is restored, an automatic data restore write cycle is started, during which the SRAM units recover their data from their corresponding MRAM units.

The invention relates to a domestic FT-C6748DSP inertial navigation resolving software online upgrading system and method, the system comprises a DSP chip, an FPGA chip, an NVSRAM FLASH chip and an SPI FLASH chip, the DSP chip is used for running an inertial navigation resolving scheme, the FPGA chip is used for collecting original pulses of an inertial navigation component and providing reset operation for the DSP chip, and the FPGA chip is used for providing reset operation for the DSP chip. The NVSRAM FLASH chip is used for storing calibration parameters and software programming control marks of a strapdown inertial navigation scheme, and the SPI FLASH chip is used for storing DSP inertial navigation resolving software. According to the method, the DSP resolving software and the inertial navigation parameters are respectively stored in the two independent chips by adopting the two FLASH, so that the effect of preventing the DSP inertial navigation resolving software from being accidentally erased and lost can be achieved, the DSP inertial navigation resolving software can be reliably started, and the reliability of the DSP inertial navigation resolving software is improved. By adopting the technical architecture designed by the invention, the problem of FLASH data loss caused by accidental power failure during FLASH erasing and writing of inertial navigation parameters can be avoided.

A storage apparatus, an electronic device, and a storage apparatus control method. A column selection circuit in the storage apparatus is coupled with an NVSRAM array; a first input / output interface circuit is coupled with an SRAM operating circuit; the SRAM operating circuit is coupled with the column selection circuit; and a nonvolatile storage operating circuit is coupled with the NVSRAM array. The nonvolatile storage operating circuit is configured to perform data backup operation on SRAM storage subunit data; and the SRAM operating circuit is configured to perform a first data read-write operation on the SRAM storage subunit data. The column selection circuit is configured to perform a data recovery operation on the nonvolatile storage subunit data, isolate operations of the SRAM operating circuit and operations of the nonvolatile storage operating circuit, and isolate the first data read-write operation, a second data read-write operation and the data recovery operation. A second input / output interface circuit is coupled with the NVSRAM array, and is configured to perform the second data read-write operation on the NVSRAM array. The storage apparatus can improve the reliability and flexibility of data read-write, backup and recovery.

Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

The invention provides a power-down data retention method and device and an embedded processor, and the method comprises the steps: responding to a power-down signal, storing power-down protection data to a random access memory, and generating a corresponding state matrix which describes the storage information of the power-down protection data in the random access memory; storing the state matrix in a nonvolatile static random access memory; and in response to the re-power-on signal, recovering the power-down protection data by loading a state matrix in the non-volatile static random access memory. By combining the advantages of the NVSRAM and the Flash, the hardware cost is reduced, and the data storage reliability and recovery efficiency are improved.

This invention relates to the field of data storage technology, providing an 8.5T non-volatile random access memory (NVSRAM) cell, a memory, and a data storage method. It combines 6T SRAM cells connected to an isolation transistor to form an NVSRAM cell. This method uses fewer transistors, has a smaller chip area, and achieves high cell storage density. The data retrieval process of the NVSRAM cell does not require power-down of the SRAM cell, discharge of the data nodes, or power-on of the SRAM cell. The retrieval process is completed simply by writing data 0 to the data nodes QB of all SRAM cells, writing data 1 to the data nodes Q, and then opening the isolation transistor to write the data from the FLASH cell to the SRAM cell. This retrieval method is simple and efficient, simplifies the design of related peripheral circuits, and effectively reduces the chip manufacturing cost of NVSRAM.

A non-volatile static random access memory (NVSRAM) includes at least one array of NVSRAM cells. And each NVSRAM unit comprises an SRAM unit and an MRAM unit. The SRAM cell includes at least six transistors, and the MRAM cell includes at least two transistors and two magnetic tunnel junction (MTJ) structures. The SRAM cell is accessed during a normal read-write operation, which enables the NVSRAM cell to achieve fast access, has infinite durability, and does not have a read-write error rate problem. In the NVSRAM unit which is not accessed by the normal read-write operation, the hidden MRAM write operation can be manually or automatically activated to back up the data stored in the corresponding SRAM unit. When the NVSRAM device is powered off, data stored in the SRAM unit may be lost, while data backed up in the corresponding MRAM unit may be retained. When power is resumed, an automatic data recovery write cycle will be initiated during which the SRAM cell recovers its data from its corresponding MRAM cell.

The invention belongs to but not limited to the technical field of aviation power distribution systems, and particularly relates to a data recording unit and method suitable for an aviation power distribution system, and the data recording unit comprises a DSP module which is connected with a FLASH module and an NVSRAM through an address bus and a data bus; the FPGA module is respectively connected with the FLASH module and the NVSRAM module and outputs a control signal; the FLASH module is used for recording detailed fault data; the NVSRAM is divided into four regions; the A area is a key information storage area, and the storage content comprises software configuration information, version information, an NVSRAM important fault information record tail pointer, a data record tail pointer before fault occurrence, an NVSRAM fault data cache record tail pointer, an NVSRAM fault data cache record head pointer and a FLASH fault data record tail pointer; the area B is an important fault information storage area; the area C is a data cache area 500 ms before the fault; and the area D is a detailed fault data cache area.

The present invention discloses an nvsram storage cell based on a 9T1C structure, an operation method thereof, and a memory, including a 6T structure and a 3T1C structure. The 6T structure is the basic storage cell of SRAM and is used for data input and storage of data 0 or 1. The 3T1C structure is used to perform data backup operations when the 6T structure is powered off, store the data in the 6T structure, perform data recovery on the 6T structure after the 6T structure resumes power, and rewrite the data back to the storage cell of the 6T structure. By controlling the plate line signal (PL) through an NMOS transistor, the influence of the PL signal on the ferroelectric capacitor can be avoided when working under this structure, ensuring the stability of the ferroelectric capacitor and reducing power consumption. By isolating the NVM and SRAM with an NMOS transistor at the storage node of the SRAM, the problem of direct current short-circuit current is avoided, the influence of the NVM on the SRAM is relatively small, the storage power consumption is reduced, and the stability of the SRAM working mode is ensured at the same time. NMOS transistors are added at both Q / NQ of the SRAM, maintaining the symmetry of the SRAM storage cell and avoiding the mismatch problem.

Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

The invention discloses a storage unit based on an RRAM and a nonvolatile storage driving circuit. A storage is formed by a 14T2R-NVSRAM storage unit based on the RRAM and the nonvolatile storage driving circuit. The 14T2R-NVSRAM storage unit comprises an SRAM module and an RRAM module, the SRAM module supports rapid reading and writing of data, and compared with a traditional 6T-SRAM, a set of control switches is added, and the fault conduction risk between the SRAM module and the RRAM module can be effectively reduced. And the RRAM module is used for realizing nanosecond backup and recovery of SRAM data and solving the problem of data loss after power failure. The nonvolatile storage drive circuit comprises a power supply detection circuit and a control signal generation circuit, the power supply detection circuit realizes automatic power-down backup and power-on recovery of data, and the signal generation circuit is responsible for generating control signal waveforms and time sequence control required in the data backup and recovery process.

Provided in the embodiments of the present disclosure are a storage apparatus, an electronic device, and a storage apparatus control method. The storage apparatus comprises: an NVSRAM array, an SRAM operation circuit, a non-volatile storage operation circuit, an error detection and correction circuit, an input / output interface circuit and a column selection circuit, wherein the error detection and correction circuit is coupled to both the input / output interface circuit and the SRAM operation circuit, the SRAM operation circuit is coupled to the column selection circuit, the column selection circuit is coupled to the NVSRAM array, and the non-volatile storage operation circuit is coupled to the NVSRAM array; the error detection and correction circuit is configured to encode and decode data transmitted between the input / output interface circuit and the SRAM operation circuit, so as to determine whether an error is present in the data and perform error correction; and the column selection circuit is configured to isolate an operation of the SRAM operation circuit from an operation of the nonvolatile storage operation circuit, and isolate a data read / write operation from a data recovery operation. The storage apparatus can improve the reliability of data read / write, backup and recovery.

A computation apparatus includes: a plurality of nvSRAM cells; and a controller configured generating an artificial intelligence computation result per currents flowing through the nvSRAM cells, wherein each nvSRAM cell includes a first partial cell including: a differential circuit including first and second inverters; a first access transistor having a drain connected to the first output node; a second access transistor having a drain connected to the second output node; a first MRAM cell including a first selection transistor and a first magnetic tunnel junction connected in series between a CBL node and the first output node; and a second MRAM cell including a second selection transistor and a second magnetic tunnel junction connected in series between the CBL node and the second output node.