3 results about "NvSRAM" patented technology

This invention relates to the field of data storage technology, providing an 8.5T non-volatile random access memory (NVSRAM) cell, a memory, and a data storage method. It combines 6T SRAM cells connected to an isolation transistor to form an NVSRAM cell. This method uses fewer transistors, has a smaller chip area, and achieves high cell storage density. The data retrieval process of the NVSRAM cell does not require power-down of the SRAM cell, discharge of the data nodes, or power-on of the SRAM cell. The retrieval process is completed simply by writing data 0 to the data nodes QB of all SRAM cells, writing data 1 to the data nodes Q, and then opening the isolation transistor to write the data from the FLASH cell to the SRAM cell. This retrieval method is simple and efficient, simplifies the design of related peripheral circuits, and effectively reduces the chip manufacturing cost of NVSRAM.

The invention discloses a storage unit based on an RRAM and a nonvolatile storage driving circuit. A storage is formed by a 14T2R-NVSRAM storage unit based on the RRAM and the nonvolatile storage driving circuit. The 14T2R-NVSRAM storage unit comprises an SRAM module and an RRAM module, the SRAM module supports rapid reading and writing of data, and compared with a traditional 6T-SRAM, a set of control switches is added, and the fault conduction risk between the SRAM module and the RRAM module can be effectively reduced. And the RRAM module is used for realizing nanosecond backup and recovery of SRAM data and solving the problem of data loss after power failure. The nonvolatile storage drive circuit comprises a power supply detection circuit and a control signal generation circuit, the power supply detection circuit realizes automatic power-down backup and power-on recovery of data, and the signal generation circuit is responsible for generating control signal waveforms and time sequence control required in the data backup and recovery process.

A computation apparatus includes: a plurality of nvSRAM cells; and a controller configured generating an artificial intelligence computation result per currents flowing through the nvSRAM cells, wherein each nvSRAM cell includes a first partial cell including: a differential circuit including first and second inverters; a first access transistor having a drain connected to the first output node; a second access transistor having a drain connected to the second output node; a first MRAM cell including a first selection transistor and a first magnetic tunnel junction connected in series between a CBL node and the first output node; and a second MRAM cell including a second selection transistor and a second magnetic tunnel junction connected in series between the CBL node and the second output node.