Digital triggering system of oscilloscope

Abstract

The invention provides a digital triggering system of an oscilloscope. An ADC module is used for converting analog signals from an analog channel of the oscilloscope into digital signals. A data reconstitution module is used for receiving four 8-bit 625 Mbps data streams output by the ADC module in parallel and outputting x(n) to an up-sampler module in a buffering storage mode. The up-sampler module is used for receiving signals x(n) of the data reconstitution module, so that pixel points of a screen and waveform sampling points are kept consistent. A digital comparator compares signals y(n) output by an up-sampler with a specified triggering threshold value ranging from 0 to 255, an output level is changed, and triggering signals are output. By the adoption of the scheme, the digital triggering system is completely achieved in an FPGA; by the adoption of the digital interpolation mode, the precision of time interval measurement is improved, triggering jittering of the oscilloscope is reduced, and the processing speed and the refresh rate are greatly increased under the circumstance that digital post-processing compensation for jittering is not needed.

Description

technical field [0001] The invention belongs to the technical field of digital oscilloscope testing, in particular to a digital oscilloscope trigger system. Background technique [0002] In the traditional analog trigger system, signal acquisition and triggering are divided into two paths. Since the delay and amplitude of the two paths are different, there will always be jitter changes in the display results at the trigger point; at the same time, most analog trigger systems use analog comparison. Comparator and high-speed logic gate circuit implementation, the layout area of ​​the device is large, the heat generated by the device is high, and the power consumption of the whole machine is large; due to the influence of noise signals, the traditional analog comparator needs to add a hysteresis circuit to obtain a stable display waveform, but there are limitations The trigger sensitivity of the analog trigger system is improved. [0003] The trigger system of a digital oscill...

AI Technical Summary

Problems solved by technology

Inaccurate TDC measurement results will cause individual displayed waveforms to deviate from the trigger point

Random components of TDC error cause this offset to vary on each trigger event, causing trigger jitter

[0007] The main problems of the analog trigger system are that the trigger jitter always exists, and it is closely related to the hardware circuit; even if a part of the jitter is compensated through digital post-processing, the processing speed and refresh rate are greatly reduced; the stable trigger of the noise signal, The analog trigger system is required to achieve a certain hysteresis around the trigger threshold, however, for small amplitude signals, a large hysteresis will limit the sensitivity of the analog trigger system

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