Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters

A technology of analog-to-analog converter, equipment, applied in the field of digital/analog converter

Active Publication Date: 2011-07-06
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These tones limit the Spurious Free Dynamic Range (SFDR) of the DAC device

Method used

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  • Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters
  • Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters
  • Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters

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Embodiment Construction

[0020] Reference is now made to the drawings, which schematically illustrate details of specific example embodiments. In the drawings, the same elements will be represented by the same numerals, and similar elements will be represented by the same numerals with different lowercase letter suffixes.

[0021] refer to figure 1 , which depicts a schematic block diagram of a single-loop sigma-delta digital-to-analog converter (DAC) with a multi-bit quantizer. A sigma-delta DAC generally indicated by numeral 100 includes a single-loop sigma-delta M-bit modulator 102 , an M-bit-to-analog converter 104 and an analog low-pass filter 106 . The sigma-delta modulator 102 includes a digital loop filter 110 and a fixed resolution quantizer 108 . Sigma-delta modulator 102 may also use multiple feedback loops in its design.

[0022] Fixed-resolution quantizer 108 processes L-bit words at its input and provides M-bit words at its output (where L>=M). Fixed-resolution quantizer 108 typical...

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Abstract

A multi-bit (M-bit, M>1 ) Sigma-Delta digital-lo-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M-N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital trunealor or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Description

[0001] Related Application Cross Reference [0002] This application claims priority to the following patent application: Philippe Deval, Vincent Quiquempoix, and Alexandre Barreto, filed October 23, 2008 filed commonly-owned U.S. Provisional Patent Application Serial No. 61 / 107,820, entitled "Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Digital-to-Analog Converters" Bit Sigma-Delta Digital-to-Analog Converters); and are hereby incorporated by reference herein. technical field [0003] The present invention relates to digital-to-analog converters (DACs), and more particularly to a sigma-delta DAC with an M-bit resolution quantizer with rounding relative to a random or pseudo-random sequence. to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the sigma-delta DAC. Background technique [0004] Today, digital-to-analog converters (DACs) are widely used in consumer, medical, industrial, and other electronic applicat...

Claims

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Application Information

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IPC IPC(8): H03M3/04
CPCH03M3/33H03M3/424H03M3/00
Inventor 菲利普·德瓦尔文森特·奎奎姆普瓦亚历山大·巴雷托
Owner MICROCHIP TECH INC
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