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Method and apparatus for dithering in multi-bit sigma-delta analog-to-digital converters

A digital converter and equipment technology, applied in the field of automatic dynamic jitter, to achieve the effect of high-efficiency pitch scrambling

Active Publication Date: 2011-08-24
MICROCHIP TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These tones can limit the device's spurious-free dynamic range (SFDR) and thus the device's signal-to-noise and distortion ratio (SINAD) (which is usually a rational fraction )

Method used

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  • Method and apparatus for dithering in multi-bit sigma-delta analog-to-digital converters

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Embodiment Construction

[0039] Reference is now made to the drawings, which schematically illustrate details of specific example embodiments. In the drawings, the same elements will be represented by the same numerals, and similar elements will be represented by the same numerals with different lowercase letter suffixes.

[0040] refer to figure 1 , which depicts a multi-bit or multi-level (nlev levels, nlev>2, M bits, M=Floor(log2(nlev)), M>1) single-loop sigma-delta analog / digital with a fixed quantizer Schematic block diagram of a converter (ADC). A multi-level (nlev) sigma-delta ADC (also called multi-bit, since encoding the levels requires more than 1 bit, M > 1) with a fixed quantizer, generally indicated by numeral 100, includes an input voltage summing node 118 , a loop filter 116 , a fixed multi-bit quantizer 120 , a multi-digit-to-analog converter (DAC) 114 and a digital decimation filter 108 .

[0041] Digital filter 108 receives sampled digital bitstream 112 and decimates digital bits...

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Abstract

A multi-bit (M-bit, M> 1 ) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Description

[0001] Related Application Cross Reference [0002] This application claims priority to the following patent application: Philippe Deval, Vincent Quiquempoix, and Alexandre Barreto, filed October 23, 2008 filed commonly-owned U.S. Provisional Patent Application Serial No. 61 / 107,820, entitled "Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Digital-to-Analog Converters" Bit Sigma-Delta Digital-to-Analog Converters)" and are hereby incorporated by reference herein; and related to the following patent applications: Philip de Waal, Vincent Quackpix, and Alexandre Barreto in 2009 Commonly owned U.S. Provisional Patent Application Serial No. 12 / 571,892, filed October 1, 1999, entitled "Method and Apparatus for Dithering in Multi-Bit Sigma-Delta Digital-to-Analog Converters" Apparatus for Dithering in Multi-Bit Sigma-Delta Digital-to-Analog Converters)". technical field [0003] The present invention relates to analog-to-digital converters (ADCs), and more particularl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M3/00
CPCH03M3/33H03M3/424H03M3/00
Inventor 菲利普·德瓦尔文森特·奎奎姆普瓦亚历山大·巴雷托
Owner MICROCHIP TECH INC
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