Development board of network multi-core processor on test board based on four field programmable gate arrays (FPGA)

Abstract

The invention discloses a development board of a network multi-core processor on a test board based on four field programmable gate arrays (FPGA). Four FPGA chips are interconnected to form an entire interconnected structure; each FPGA chip is provided with a GTX transmission channel and a GPIO transmission channel which are respectively connected with the other three FPGA chips; and each FPGA chip is provided with a power management module, a board level clock drive module and a memory system. Date input and output ports of the development board are respectively arranged on the second and the fourth FPGA chips; and the data input and output ports are full-duplex differential 2.5Gbps fiber interfaces. The emulated memory bandwidth of the development board reaches 759.2Gbps which is far from being achieved by the current circuit designs of the other development boards with multiple FPGAs; with the interconnection of the chips, the throughput is above 30Gbps; and the development board provides enough hardware resource for FPGA hardware designers so as to test and realize the design of a prototype chip of a VL (very large) multi-core processor based on NoC.

Description

technical field [0001] The invention relates to integrated circuit technology, which is a development board for multi-core network processor design / verification, suitable for VLSI software-hardware collaborative design verification, and a platform for on-chip network multi-core processor software-hardware collaborative test verification, specifically a A development board for verifying a network-on-chip multi-core processor based on four FPGAs. Background technique [0002] Since single-chip processors based on traditional System-on-Chip (SoC) face major problems in terms of core frequency, on-chip communication, power consumption, and area, multi-core processors based on Network-on-Chip (Network-on-Chip) The processor came into being, and solved many problems faced by the former from the architecture. The NoC interconnect structure has the advantages of parallel communication between IPs, good scalability, and high throughput, and solves the architectural problems of multi...

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Problems solved by technology

[0004] The problem to be solved by the present invention: the existing single-chip FPGA development board cannot meet the requirements of hardware resources required for VLSI design, and the design of the development board is faced with how to expand the hardware resources of the development board to meet the requirements of NoC's multi-core processor for imitation and storage. Inter-chip data communication throughput requirements, and ensure the stable operation of the development board

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