Security RAM block with multiple partitions

Abstract

The disclosure relates to a security RAM block with multiple partitions. Circuits, methods, and apparatus for storing application data, keys, authorization codes, or other information in a volatile memory on an FPGA. A field programmable gate array (FPGA) can include multiple memory blocks and partition those blocks among multiple independent reconfigurable regions. Access to the memory blocks can then be restricted so that only authorized regions have access to particular memory partitions. In addition, each partition can store multiple message authentication codes (MACs) for further controlling access to data in each partition.

Description

[0001] Cross References to Related Applications [0002] This application is a continuation-in-part of U.S. Patent Application Serial No. 12 / 830,447, filed June 6, 2010, which was filed September 7, 2006, entitled "SECURITY RAM BLOCK" US Patent Application No. 11 / 517,689 (now US Patent No. 7,752,407), all of which are incorporated herein by reference in their entirety. Background technique [0003] The present invention relates generally to storing data on integrated circuits, and more particularly to protecting data stored in battery-backed memory on field programmable gate arrays (FPGAs). [0004] The circuit complexity and tasks performed by integrated circuits, such as field programmable gate arrays, have increased enormously over the past few years. Highly complex software or applications configured to perform complex user-defined functions run on programmable logic elements. [0005] Typically, these applications require data to be stored in memory, eg, applications m...

AI Technical Summary

Problems solved by technology

If the key is stored in memory for use during decryption, it is desirable to protect and restrict access to the key

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