Method using FPGA (field programmable gate array) for controlling DSP (digital signal processor) program load running

Abstract

A method using an FPGA (field programmable gate array) for controlling DSP (digital signal processor) program load running, which includes the steps: 1 selecting a chip with a power output enable end EN to supply power to a DSP; 2 connecting a certain IO (input / output) pin of the FPGA to the enable end EN, and temporarily naming the IO pin as IO pin CONTRL_EN; and 3 editing FPGA codes, and enabling the IO pin CONTRL_EN to continuously output low level after FPGA loading is completed. The method has the advantages of simplicity, capability of leading design and debugging of a circuit to be simpler and easier and high flexibility and reliability. Particularly when a plurality of DSPs are connected with the FPGA, the method is convenient for arbitrarily defining the electrifying load sequence and delay time of the DSPs, which cannot be realized by any special chips.

Description

technical field [0001] The invention relates to a program loading method for a digital signal processor DSP and a large-scale programmable logic device FPGA, in particular how to avoid conflicts during loading and realize independent and reliable loading. Background technique [0002] Field programmable device FPGA is a device widely used in recent years. It has the characteristics of high integration, small size, low power consumption, high reliability, high security, low system cost, good flexibility and easy connection. Therefore, it is widely used in modern Widely used in electronic technology. In embedded system hardware design, FPGA and digital signal processor DSP are often connected together to make full use of the rich IO resources in the FPGA chip for expansion to make up for the shortcomings of DSP's strong computing power and weak control ability. [0003] There are two commonly used circuit design methods. One is to use the 8-bit or 16-bit bus buffer 245 to is...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that more components are required, the layout of the circuit board is time-consuming, and it is more troublesome in the case where the volume is sensitive

Especially when multiple FPGAs and DSPs are interconnected, this shortcoming is particularly obvious, which greatly increases the workload of circuit board layout and significantly reduces system reliability.

The other is to use a special power-on sequence control chip to load different DSPs. The disadvantage of this method is that the power-on sequence is controlled by a dedicated chip and cannot be changed at will. It is very inflexible. Once it is done, it cannot be changed and cannot satisfy users. diverse needs

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