Data communication method between processors and FPGA (field programmable gate array) equipment

A data communication and processor technology, applied in the field of data communication, can solve the problems of low real-time data exchange, slow access speed, complex dual-port RAM control logic, etc., and achieve the effect of flexible logic implementation and high cost performance.

Inactive Publication Date: 2013-04-10
深圳市华力特电气有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the inventor found in the practice and research of the prior art that the control logic of the traditional dual-port RAM is relatively complicated, the access speed is relatively slow, and the real-time performance of data exchange is relatively low.

Method used

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  • Data communication method between processors and FPGA (field programmable gate array) equipment
  • Data communication method between processors and FPGA (field programmable gate array) equipment
  • Data communication method between processors and FPGA (field programmable gate array) equipment

Examples

Experimental program
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Embodiment 1

[0022] see figure 1 , figure 1 It is a flow chart of the method in Embodiment 1 of the present invention. Such as figure 1 As shown, a data communication method between processors may include the following steps:

[0023] 101. The FPGA reads data output from the first processor.

[0024] Wherein, the FPGA is provided with a shared data block, and in one embodiment, the shared data block can be a block random access memory BlockRam, and adopts the basic principle of a standard dual-port RAM with an intellectual property module (IP, Intellectual Propertycore) core to realize the shared data block logical function. The shared data block has write competition logic, which can effectively avoid being written by mistake.

[0025] The clock of the shared data block can be input by an external 16MHz oscillator through a digital clock management unit (DCM, Digital Clock Manager) after phase-locking and frequency conversion.

[0026] Further, the data output by the first processor...

Embodiment 2

[0033] see figure 2 , figure 2 It is a flowchart of the method of Embodiment 2 provided by the present invention. Such as figure 2 As shown, a data communication method between processors, including:

[0034] 201. The FPGA reads data output from the first processor.

[0035] Wherein, the internal structure principles and logic functions of the FPGA can refer to the description in Step 101 of Embodiment 1, and the embodiments of the present invention will not be repeated here.

[0036] 202. Receive an identifier sent by the first processor.

[0037] Wherein, the identifier is sent by the first processor after the FPGA finishes reading the data output by the first processor. The identification is used to trigger the step of FPGA writing an interrupt signal to the second processor (that is, step 203 in this embodiment).

[0038] In an embodiment, the identifier sent by the first processor may be read by the shared data block of the FPGA, and the identifier may be 0x55AA....

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Abstract

The embodiment of the invention provides a data communication method between processors and FPGA (field programmable gate array) equipment. Data output from a first processor is read by FPGA; an interruption signal is written into a second processor; and the second processor reads data which is output from the first processor and is read from the FPGA. Compared with the prior art that the communication mode between the processors is realized by a double-port RAM (random-access memory) chip, the communication method provided by the invention has the characteristics that data can be exchanged in time, logic realization is more flexible, and the cost performance is higher.

Description

technical field [0001] The invention relates to data communication technology, in particular to a data communication method between processors and FPGA equipment. Background technique [0002] The traditional dual-port random access memory (RAM, random access memory) chip implements dual-processor communication by providing two sets of completely independent data lines, address lines, and read-write control lines on one memory, and allowing two independent Memory to which the processor system simultaneously accesses randomly. [0003] However, the inventor found in the practice and research of the prior art that the control logic of the traditional dual-port RAM is relatively complicated, the access speed is relatively slow, and the real-time performance of data exchange is relatively low. Contents of the invention [0004] Embodiments of the present invention provide a data communication method between processors and Field-Programmable Gate Array (FPGA, Field-Programmabl...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163
Inventor 董光府郭彩霞文小龙张应榜
Owner 深圳市华力特电气有限公司
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