User register state capture circuit adopting single-event hardened FPGA (field programmable gate array)

Abstract

A user register state capture circuit adopting a single-event hardened FPGA (field programmable gate array) comprises a user register, a transistor M3, a transistor M4, an SRAM (static random-access memory) storage unit and a capture signal generation circuit, wherein the transistor M3 and the transistor M4 are arranged between the user register and the SRAM storage unit; the capture signal generation circuit generates an output signal CAPTURE, controls conduction of the transistor M3 and the transistor M4 and realizes data capture readback. Compared with the prior art, the state capture circuit has the advantages that through capture readback operation, dynamic partial reconfiguration can be performed if the condition that configuration bit stream stored in the CSRAM (custom SRAM) has single-event upset is discovered, corresponding logic can be reset if the state of the SRAM storage unit for storing the captured user register state in the CSRAM has an error, so that the single-event upset accumulation effect of an FPGA chip is reduced remarkably.

Description

Technical field [0001] The invention relates to a technology for capturing values ​​in a user register, in particular to a single-event reinforced FPGA user register state capturing circuit. Background technique [0002] Such as figure 1 Shown is the structure of the field programmable gate array FPGA. The input and output ports (IOB) are located around the chip, the configurable logic module (CLB) is arranged in an array inside, and the block memory (BRAM) is interspersed in the configurable logic module (CLB). In ), FPGA also includes configuration logic, configuration interface and other components, such as programmable interconnect structure and configuration memory array (CSRAM) spreading over the entire FPGA chip, connecting various modules. [0003] The SRAM FPGA chip does not have any logic function before configuration. It completes the function configuration by loading the configuration data specified by the user application into the internal configuration memory array (C...

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Problems solved by technology

[0004] When the FPGA chip is used in the space radiation environment, the space high-energy particles passing through the FPGA will cause an instantaneous current on the circuit node, causing the configuration storage unit SRAM in the configuration memory array to undergo a single-event flip, and the circuit in some areas will produce local functional errors. , short circuit or open circuit of the interconnection wire, making the circuit in this area unable to work normally

[0005] At present, it is possible to judge whether the configuration memory array in the FPGA chip has a single-event flip by reading back the configuration memory array technology during space application, and then use the partial reconfiguration technology to repair the system function, but the disadvantage of this technology is that it cannot know the state of the user logic , when the single event flip of the SRAM unit in the configuration memory array has caused an operation error in the logic of the CLB and IOB, in addition to partial reconfiguration, it is also necessary to perform partial reset processing on the wrong logic part, so in order to accurately know the current state of the user logic , requires a capture circuit capable of obtaining the state of the user registers

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