Testing device based on FPGA (field programmable gate array)

Abstract

The invention discloses a testing device based on FPGA (field programmable gate array). The corresponding testing device which is designed innovatively through an FPGA circuit and adjustability of an output and input standard and a mode replaces corresponding electronic circuits of an existing testing device. The performance is greatly improved, and meanwhile, the power consumption of the circuit and the physical size and the cost of key design are greatly reduced. Additionally, the high-speed data transmission performance of the FPGA is innovatively used for transmitting a large quantity of test data to a device directly connected with a tested element at a high speed, and one of the bottlenecks of miniaturization of the key design is eliminated. Further, a circuit related with a direct-current and low-speed performance test and a high-speed test circuit are completely separated and are connected with the tested element during the test of each of the circuits, so the two circuits are not mutually influenced; the circuits are connected when the circuits need to be connected together for a corresponding test. Therefore, the power consumption, the physical size and the cost are greatly reduced, and the testing device has a good market popularization and utilization prospect.

Description

technical field [0001] The present invention relates to the technical field of electronic testing, and more specifically, to an FPGA-based testing device. Background technique [0002] The integrated circuit testing equipment includes a circuit for driving the device under test and receiving the output signal of the device under test. In the prior art, it is realized with specially designed special electronic devices. It has the following disadvantages: [0003] 1. Because it is specially designed and manufactured for this purpose, its usage is small, so the design and manufacturing costs are extremely high; [0004] 2. Because the driving and receiving voltages are continuously controllable and adjustable, it is very difficult to achieve high speed, and due to the large power consumption, it cannot be miniaturized due to heat dissipation. [0005] In addition, the controllable delay circuit used to adjust the timing of each channel in the prior art uses split elements, w...

AI Technical Summary

Problems solved by technology

It aims to solve the problems of excessive power, difficulty in miniaturization, and high manufacturing cost of existing integrated circuit testing equipment

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