Device and method for field programmable gate array (FPGA) single event effect dynamic fault testing

Abstract

The invention relates to a device for field programmable gate array (FPGA) single event effect dynamic fault testing. The device comprises a control circuit module (11), an upper computer control module (12), a controllable pulse laser module (15) and a three-dimensional mobile module (16), wherein the three-dimensional mobile module (16) is used for installing a tested FPGA device (13) to be tested during the testing; the upper computer control module (12) is connected with the control circuit module (11), and the control circuit module (11) is connected to the controllable pulse laser module (15). During the testing, the control circuit module (11) is further connected with the tested FPGA device (13) and a contrast tested FPGA device (14) corresponding to the tested FPGA device (13).

Description

technical field [0001] The invention relates to a single event effect detection device, in particular to an FPGA single event effect dynamic fault test device and method. Background technique [0002] The single event effect (Single Event Effect) refers to the incident of a single high-energy charged particle in space on a semiconductor device, generating a large number of electron-hole pairs that are collected by the sensitive area of ​​the device, causing the logic state of the device to be reversed, the stored data to be changed, and even the device to be permanently A phenomenon of ionizing radiation that damages. Common single event effects include Single Event Upset, Single Event Transient and Single Event Latch-up. [0003] Spacecrafts in space are always in a space radiation environment composed of charged particles, in which high-energy protons and heavy ions can cause single-event effects in semiconductor devices in the spacecraft electronic system, seriously affe...

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Problems solved by technology

[0005] The purpose of the present invention is to overcome the defect that the test method in the prior art does not establish the dynamic synchronization relationship between the simulation device and the device under test, thereby providing a test device and method capable of dynamically detecting FPGA single event effect faults

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