Chip testing system and method based on field programmable gata array (fpga)

Abstract

The invention discloses a chip testing system and method based on a field programmable gata array (fpga), and relates to the technical field of chip testing. The chip testing system based on the fpgacomprises a PC terminal and the fpga, wherein the PC terminal is used for applying a test incentive instruction and sending the test incentive instruction to the fpga; and the fpga is used for receiving the test incentive instruction, parsing the test incentive instruction and sending the test incentive instruction to a chip, the fpga can judge whether a test type is an IO test or a register test,the IO test comprises configuration of a chip test mode and vertical pull operation of chip IO, and the register test comprises read-write operation of a chip register. The chip testing system and method support two test types of IO and register read-write operation, users can debug test codes online, compilation time is short, and the chip testing system and method can flexibly meet various chiptesting requirements.

Description

technical field [0001] The invention relates to the technical field of chip testing. Background technique [0002] Chip test modes usually include scan, bist, analog, and IO (input / output) test modes, and different test modes correspond to different test purposes. The current chip test platform is generally based on ATE (automatic test equipment). After configuring the test mode for a specific chip test IO pin, apply a test stimulus to the chip IO, read the value given by the chip IO and compare it with the correct value. The conclusion of whether the chip is normal. However, due to the relatively expensive experimental equipment of ATE testing machines, it is difficult for ordinary laboratories to have similar testing equipment and environments. Moreover, in the traditional test mode, many tests pull the test signal to the I / O of the chip, which not only increases the complexity of the chip design for testability (DesignForTest, DFT), but also makes the I / O limited Or wh...

AI Technical Summary

Problems solved by technology

However, due to the relatively expensive experimental equipment of ATE testing machines, it is difficult for ordinary laboratories to have similar testing equipment and environments.

Moreover, in the traditional test mode, many tests pull the test signal to the I / O of the chip, which not only increases the complexity of the chip design for testability (DesignForTest, DFT), but also makes the I / O limited Or when it comes to high-speed analog (analog) IP test chips, many tests cannot be realized, because it is not impossible to put all the test signals on the chip IO pins

[0003] At the same time, in the chip test mode, traditional software debugging methods cannot be used, so it is an urgent problem to provide a low-cost, high-efficiency, and flexible configuration test system to meet the test requirements for chips.

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