14results about How to "Reduced wiring area" patented technology

The invention discloses an LED backlight driving system. The LED backlight driving system comprises a backlight time sequence controller, at least one first LED lamp panel and at least one second LED lamp panel. The first LED lamp panel and the second LED lamp panel are each provided with a plurality of driving links, the backlight time sequence controller sends a backlight brightness driving instruction to each driving link, and the backlight brightness driving instruction further comprises a first position relation instruction or a second position relation instruction; the first position relation instruction controls the driving chip to obtain a backlight brightness data packet according to a first position corresponding relation; the second position relation instruction controls the driving chip to obtain the backlight brightness data packet according to the second position corresponding relation. According to the invention, the problem that the driving sequences of the driving chips on the lamp panels are inconsistent due to the physical position relationship between the lamp panels and the backlight time schedule controller in the practical application of multiple lamp panels is solved. Therefore, backlight sequential control and the LED lamp panel can be configured on the LED backlight panel more flexibly, and the wiring area is greatly saved.

The invention relates to an access control method and device of a storage system, the storage system and a medium, by receiving an access request sent by an access source, the access source is controlled to access a storage space corresponding to each access source in the storage system according to the access request, and the corresponding storage space comprises at least one exclusive storage unit. At least one of the exclusive storage units is only connected with one corresponding access source, and in the circuit, at least one of the exclusive storage units in the storage system is only connected with one corresponding access source in advance, so that the at least one of the exclusive storage units does not have wiring for other access sources on hardware wiring, and the access source of the storage system is not required to be accessed. Therefore, the wiring area of the circuit in the storage system on a hardware circuit layout can be effectively reduced, and the wiring difficulty of the circuit can be effectively reduced.

The invention relates to a memory cell, a memory structure and a preparation method thereof. The memory cell includes: a shared bit line extending in a first direction; a shared word line extending in a third direction, the shared word line including a write word line portion and a read word line portion; the first filling structure is located on the side wall of the write-in word line part; the write-in channel structure comprises a write-in gate dielectric layer and a write-in channel layer, the write-in gate dielectric layer extends along the side wall of the write-in word line part and each side wall of the first filling structure, and the write-in channel layer is located on the surface of the write-in gate dielectric layer; the isolation layer comprises a first isolation part, and the first isolation part is located on the side, away from the shared word line, of the write-in channel layer; the reading channel structure comprises a reading gate dielectric layer and a reading channel layer, the reading gate dielectric layer extends along the side wall of the first isolation part and the side wall of the writing channel layer, and the reading channel layer extends along the side wall of the shared bit line, the surface of the reading gate dielectric layer and the side wall of the reading word line part. According to the embodiment of the invention, the storage density can be effectively improved.

The utility model provides a grid driving control circuit, a display driving chip, a display panel and a display device. The circuit comprises a plurality of gate drive control units, each gate drive control unit comprises a decoding module, an electric balance control module, an electric balance function module and a signal output module, and the decoding module is used for outputting a decoding output signal according to a digital control signal; the electric balance control module is used for generating a function control signal according to the digital control signal and the electric balance starting signal; the electric balance function module is used for opening or closing an electric balance function according to the function control signal, and controlling the signal output module to increase an intermediate voltage between the lowest voltage and the highest voltage of the gate driving signal under the condition that the electric balance function is opened; and the signal output module is used for outputting a gate driving signal according to the decoding output signal under the condition that the electric balance function is closed, so that the area of a display driving chip is reduced.

The present invention discloses an LED driving circuit, a single-line communication device and a method, wherein the single-line communication method for an LED display system comprises: utilizing a first data port and a second data port of a plurality of LED driving circuits to cascade the plurality of LED driving circuits; utilizing a first data port of a controller to provide a driving data packet and utilizing a second data port of the controller to receive a status data packet; a front-stage LED driving circuit in the plurality of LED driving circuits forwards a front-stage status data packet and a rear-stage driving data packet to a rear-stage LED driving circuit, thereby realizing single-line control of the writing of LED driving circuit data and returning the status data to the controller, and the return data channel does not require an additional wiring channel to reduce the wiring area.

The invention provides a display panel and a display device. The display panel comprises a substrate, a first metal layer and a second metal layer which are sequentially laminated. The first metal layer comprises a first wire and a second wire, the second metal layer comprises a third wire and a fourth wire, the orthographic projection of the first wire on the substrate is at least partially overlapped with the orthographic projection of the third wire on the substrate, and the orthographic projection of the second wire on the substrate is at least partially overlapped with the orthographic projection of the fourth wire on the substrate; the two adjacent driving units in the same column are electrically connected with the wires in the different metal layers, so that the RC loads of the two adjacent columns of driving units are the same while the pixel density of the display panel is improved, and the problem of uneven display of the display panel is solved.

The utility model belongs to the technical field of numerical control attenuators, and discloses a low-phase-shift numerical control attenuator which comprises a first attenuation bit unit, a second attenuation bit unit, a third attenuation bit unit, a fourth attenuation bit unit, a fifth attenuation bit unit and a sixth attenuation bit unit which are arranged in a cascade mode. The attenuation bits of the first attenuation bit unit, the second attenuation bit unit, the third attenuation bit unit, the fourth attenuation bit unit, the fifth attenuation bit unit and the sixth attenuation bit unit are 8dB, 1dB, 0.5 dB, 2dB, 4dB and 16dB respectively, the second attenuation bit unit and the third attenuation bit unit are of a deformed T-shaped structure, and the fourth attenuation bit unit and the fifth attenuation bit unit are of a pi-shaped attenuation network structure. The sixth attenuation bit unit is of a switch path attenuator structure, and the first attenuation bit unit comprises two fifth attenuation bit units which are connected in series. The low-phase-shift numerical control attenuator has the characteristics of low insertion loss, low additional phase shift, high attenuation precision, high linearity and the like.

This invention discloses a flexible temperature and stress integrated sensor array based on shielded strips and its fabrication method, relating to the field of microelectronics technology. The array includes: a first conductive layer comprising multiple first conductive lines arranged parallel to a first direction; a second conductive layer comprising multiple second conductive lines arranged parallel to a second direction; the first and second conductive lines define multiple regions of the array, each region comprising four diagonally arranged sub-regions, each region housing two stress sensors and one temperature sensor; and a shielded strip layer located between the first and second conductive layers, comprising multiple shielded strips arranged parallel to the second direction, with the second conductive lines located on the upper surface of the shielded strips; wherein the first and second directions intersect. This invention significantly reduces the area ratio of conductive lines in traditional layouts, greatly improving the effective utilization rate of the sensing area.

The present invention discloses a DDR topology structure and a PCB board, wherein the DDR topology structure includes a main segment routing connecting a central node and a control signal transmitting end, a first DDR connected to a termination resistor through at least one termination routing, and a second DDR connected to the central node through multiple segment routings. Since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs and improve signal integrity; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared with the fly-by topology structure which is only arranged in a chain along one direction.

The application discloses a storage structure and a memory, wherein the storage structure comprises: a first storage chip and a second storage chip; the first storage chip is stacked on one side of the second storage chip, and the first storage chip and the second storage chip are connected in three dimensions; the first storage chip is provided with a plurality of pins for being connected to a preset circuit board, a signal transmission line of the first storage chip is connected with the pins, and a signal transmission line of the second storage chip is connected with the pins through the first storage chip; the storage structure is configured to read or write the first storage chip through the signal transmission line of the first storage chip after receiving a preset first chip select signal; and the storage structure is further configured to read or write the second storage chip through the signal transmission line of the second storage chip after receiving a preset second chip select signal. In the process of realizing storage capacity expansion, the application avoids increasing the wiring resources of the PCB board and reduces the packaging cost.

The invention provides a semiconductor device, a manufacturing method thereof and a memory device. The semiconductor device comprises a word line; the word lines extend along a first direction; a bit line; the bit lines extend along a second direction; the second direction intersects with the first direction; a first conductive connection structure; the first conductive connection structure is located between the first surface and the word line; one end of the first conductive connection structure is connected with the word line; the first surface and the second surface are two opposite surfaces of the semiconductor device along the first direction; a second conductive connection structure; the second conductive connection structure is located between the second surface and the bit line; one end of the second conductive connection structure is connected with the bit line.

The utility model relates to the technical field of car light circuit, specifically disclose a miniaturized integrated car light BUCK circuit, including BUCK IC integrated chip, BUCK IC integrated chip includes VIN pin, EN pin, VOUT pin, FB pin, VCC pin and BST pin, has the first capacitor group and second capacitor group on VIN pin, the first resistance formation POWER IN is connected on EN pin, the voltage -division resistance for voltage division is provided with on FB pin, VOUT pin is connected with third capacitor group, the utility model discloses a purpose at to solve the traditional car light circuit reliability problem through car light BUCK circuit, help system improves stability.

The invention relates to a memory cell, a memory structure and a preparation method thereof. The storage unit comprises a write transistor, a first transistor and a second transistor, the write transistor comprises a write word line, a write gate dielectric layer and a write channel layer, the write word line extends in a first direction, the write gate dielectric layer is located on the side wall of the write word line, and the write channel layer is located on the side wall of the write gate dielectric layer; a shared lead extending in a third direction; the first electrode and the shared wire are arranged in the first direction, and the first electrode and the shared wire are located on the same side of the write-in channel layer; the reading transistor comprises a reading gate dielectric layer, a reading channel layer and a reading bit line, the reading gate dielectric layer is located between the shared wire and the first electrode and extends to the side wall of the first electrode, the reading channel layer comprises a reading channel part, the reading channel part is located on the side wall of the reading gate dielectric layer, one end of the reading channel part is connected with the shared wire, and the other end of the reading channel part is connected with the first electrode. And the other end is connected with the reading bit line. According to the embodiment of the invention, the storage density can be effectively improved.

The utility model discloses an electronic circuit breaker and a protection circuit thereof. The electronic circuit breaker comprises a shell, a first circuit board and a second circuit board. The first circuit board is connected with the second circuit board, and the first circuit board and the second circuit board are used for laying a protection circuit. And the protection circuit can control the on-off of a line passing through the electronic circuit breaker. The shell is provided with a containing cavity, the first circuit board and the second circuit board are arranged in the containing cavity, and the second circuit board is located on one side of the first circuit board in the thickness direction. According to the scheme, the protection circuit is integrated on the first circuit board and the second circuit board, and the second circuit board is arranged on one side of the thickness direction of the first circuit board, so that the layout areas of the protection circuit are not in the same plane, the size of the circuit board is reduced, and the assembly compactness of all parts in the electronic circuit breaker is improved.