193results about How to "Reduced wiring area" patented technology

A touch-sensitive display device includes a color filter substrate, an array substrate, a liquid crystal layer, and a touch-sensing structure. The touch-sensing structure is disposed on the color filter substrate and includes at least one first sensing series and at least one second sensing series overlapped with and spaced apart from the first sensing series. During a touch-sensing operation, the first sensing series receives a common voltage scanning signal, and the second sensing series receives a sensing signal to sense coupling capacitance formed as a result of a touch action when the common voltage scanning signal drives the first sensing series.

It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body.

The invention relates to the field of display technology, and particularly relates to a shift register unit and a driving method, a gate driving circuit as well as a display device thereof. Through arranging a voltage stabilizing capacitor which is connected with a pull-up node, the shift register unit provided by the embodiment of the invention stabilizes an electric potential at the pull-up node by using the voltage stabilizing capacitor, so that signals output by the shift register unit are more stable. Meanwhile, the shift register unit is composed of a small amount of transistors and capacitors, so that the wiring area of the gate driving circuit is greatly reduced, and a technical support is provided for designing a liquid crystal display device with a narrower border; in addition, the structure of the gate driving circuit is simplified, so that the manufacturing technology of the gate driving circuit is simplified, and the manufacturing cost is reduced. Furthermore, the shift register unit provided by the invention also fast and effectively pulls down the output signals to be a low electric potential through two pull-down processes; and the pull-down capacity of the gate driving circuit is strengthened.

A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.

The present invention is to provide a wiring of a touch panel comprising a glass substrate including a transparent and conductive layer on a top surface; a plurality of wires disposed along a border of the glass substrate; a plurality of conductive ends formed at the top side of the glass substrate, each of the wires being electrically connected to one of the conductive ends; and a flexible circuit board provided at the wires, the flexible circuit board including a plurality of connections each electrically connected to one of the conductive ends. By utilizing this wiring, prior used conductors are replaced by the flexible circuit board in order to decrease wiring area and make wiring of the touch panel become narrower.

The invention discloses a touch drive circuit, an optical embedded touch screen and a display device, wherein the touch drive circuit comprises a light sensitive submodule, a data writing submodule, a drive submodule and a control submodule. Under the control of a scanning signal terminal, the data writing submodule transmits a scanning signal of the scanning signal terminal to the drive submodule; when the drive submodule is controlled to be opened by the scanning signal, the drive submodule outputs a touch sensing signal to the control submodule, and the touch sensing signal is reduced with increasing of light intensity of the light sensitive submodule; and under the control of a control signal terminal, the control submodule inputs the touch sensing signal to a touch signal reading terminal, so that the touch function is realized. Compared with a drive circuit of a conventional optical embedded touch screen, the control submodule is used for controlling the drive submodule to transmit the touch sensing signal to the touch signal reading terminal, and when the touch signal reading terminal of each level of drive circuits is connected with the same touch signal reading wire, signals output by different levels of drive circuits can be prevented from mutual crosstalk.

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

A CMADS circuit is characterized in that one transmitter is able to drive a plurality of receivers at a high rate to make each of the receivers have a low amplitude. A signal line driving integrated circuit has input terminals formed along one side (for example, left side) of the integrated circuit for receiving each signal via each of CMADS bus lines and output terminals formed along an opposing side (right side) opposite the one side. The input and output terminals are disposed such that a distance from each of the input terminals to a side (lower side) of the integrated circuit along which the signal voltage output terminals are disposed becomes equal to that from each of the output terminals disposed to individually correspond to the input terminals to the lower side. Accordingly, a CMADS bus is formed penetrating the inside of the signal line driving integrated circuit. In a case where a CMADS bus couples a plurality of signal line driving integrated circuits in series, the CMADS bus signal lines constructed as described above can travel throughout a series of the signal line driving ICs without jackknifing at around connection portions between the adjacent integrated circuits, thereby substantially eliminating an entire part of a wiring area required for the conventional LCD device and realizing a small-sized LCD device.

The invention provides a grid drive circuit and a grid drive method. The grid drive circuit comprises a grid drive module (2 or 2') and a plurality of multiplexer modules (4 or4'). The multiplexer modules (4 or4') are electrically connected with corresponding signal output ports (20 or 20') and comprise low-level input ends (VGL or VGL') and first, second and third signal output ends (43, 44 and 45 or 43', 44' and 45'), wherein the first, second and third signal output ends (43, 44 and 45 or 43', 44' and 45') are used for being electrically connected with a panel of a Tri-gate framework. The multiplexer modules (4 or4') control the first, second and third signal output ends (43, 44 and 45 or 43', 44' and 45') to be electrically connected or disconnected with the low-level input ends (VGL or VGL') of the multiplexer modules (4 or4') or the corresponding signal output ports (20 or 20'). The invention further provides the corresponding grid drive method. According to the grid drive circuit and method, the number of Tri-gate mode grid drive devices can be reduced greatly, and the boundary wiring area of the panel can be reduced.

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

A transfer circuit 25 includes two sets of an input circuit 52A and an output circuit 53B, which allows bidirectional transfer. The input circuit 52A decomposes external input data signals DI11A and DI12A to signals on lines L11 to L14 in synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuit 53B composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DO11B and DO12B. Signals on either the lines L11 to L14 or L21 to L24 are selected by a multiplexer 57 to provide to a main body circuit.

This present invention provides a liquid-crystal panel that presents a high-density wiring while maintaining reliability of the wiring. Odd-numbered scanning lines are connected to a first wiring group while even-numbered scanning lines are connected to a second wiring group. Each of the scanning lines is supplied with a scanning signal the polarity of which is inverted every horizontal scanning period. Among wirings forming the first wiring group and the second wiring group, a line-to-line voltage between any adjacent wirings becomes zero volt for a majority of the time. Accordingly, degradation of the wirings due to electrolytic corrosion is controlled even if the spacing between the wirings is narrowed.

The invention provides an array substrate and a preparation method thereof, and a touch control display panel. The array substrate comprises a first electrode and a second electrode for transmitting display signals, and a touch control wire for transmitting touch control signals, the first electrode and the touch control wire are respectively arranged in different layers, and orthographic projections of the first electrode and the touch control wire on the substrate are overlapped. According to the array substrate and the preparation method thereof, and the touch control display panel, the first electrode and the touch control wire are respectively arranged in different layers, and the orthographic projections of the first electrode and the touch control wire on the substrate are overlapped so that the lightproof wiring area is reduced, a light-transmission region is increased, the aperture ratio is increased to the maximum, and the brightness is increased; besides, the first electrodeis adopted as a light-shielding structure so that the area of a light-shielding layer is reduced, the light-transmission region is further increased, adverse display caused by factors including the aligning precision during preparation is effectively avoided, and the yield is increased.

The present invention relates to a semiconductor device in which a power supply circuit is disposed on an array substrate, which achieves reduction of the size by suppressing an increase of the area occupied by the power supply wiring. The feature of the present invention is that a power supply circuit is disposed adjacent to a supply voltage input terminal and a signal line driving circuit. An extremely large amount of electric current is flown in a power supply wiring between the power supply circuit and the supply voltage input terminal and a power supply wiring between the power supply circuit and the signal line driving circuit. Thus, by disposing the power supply circuit adjacent to the supply voltage input terminal and the signal line driving circuit, the power supply wirings therebetween can be shortened. Accordingly, the wiring resistance proportional to the product of the length and the width becomes small so that the thinned power supply wiring can be tolerated. As a result, the power supply wirings can be shortened and thinned so that the wiring area can be decreased.

A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

The invention discloses a display panel and a display apparatus, and aims to weaken edge sawtooth of a displayed image of the display panel, improve the display quality of the display panel and reducethe wiring area of a gate driving circuit occupied in a non-display region, thereby realizing a smaller frame area of the display panel. The display panel comprises a display region and a non-displayregion; the display region comprises a plurality of pixel units; each pixel unit comprises a first electrode, a second electrode arranged opposite to the first electrode, and a light emitting layer positioned between the first electrode and the second electrode; the display region comprises a central display region and an edge display region; and the first electrode in the pixel unit positioned in the edge display region is at least electrically connected with one first electrode in the pixel unit in the central display region, wherein the gate driving circuit is arranged below at least one first electrode of the pixel unit in the edge display region.

A welding wire for use in electric arc welding and method of making same, wherein the wire has an effective outer diameter and comprises a length of solid metal formed into a series of distinct segments each having a selected volume and having a narrow region and non-narrow region with the cross sectional area of the solid metal at said non-narrow region being greater than the cross sectional area of the solid metal at the narrow region.

A semiconductor package having an impedance matching device is disclosed, which is especially applicable to conventional system-in-package structures and system packaging design with high-density I / O design. The impedance matching device achieves impedance matching between a semiconductor chip and a signal transmission wiring on the substrate or between different systems integrated in the semiconductor package by employment of a vertical conductive line or combination of a vertical conductive line and a stub transmission line. The vertical conductive line is electrically connected with the signal transmission wiring on the substrate at one end thereof, and the stub transmission line may be further connected to the other end of the vertical conductive line. This impedance matching device helps to effectively reduce the wiring area of an impedance matching network of the semiconductor package and enhance the flexibility and interchangeability in layout of the wiring.

This liquid crystal display device allows outputs from RS-FF circuits (401 to 409) and switch circuits (411 to 419), which function as a shift register, to be provided as scanning signals that are selectively activated during odd and even scanning line selection periods, by simply changing the potential of an enable signal (EN) (i.e., by simply providing an EN signal line), which achieves interlacing drive that allows a reduction in the number of polarity inversions, thereby making it possible to reduce power consumption and a wiring area for control lines and achieve simple control which allows circuit simplification, resulting in a reduced frame area and a display panel which is compact as a whole.

The image display apparatus is provided with a dot matrix of light emitting devices, driver circuitry, and switching circuitry. The dot matrix is a plurality of light emitting devices arranged in an in-line by n-column matrix, and one terminal of each light emitting device in each line is connected to a common source line. Driver circuitry controls light emitting devices active or inactive depending on an input illumination signal. In the active state, switching circuitry floats common source lines, and in the inactive state, discharges all common source lines to ground.

A Liquid crystal display device and manufacturing method thereof are provided. According to an exemplary embodiment of the present disclosure, an LCD device includes: a first substrate including a display area and a non-display area disposed outside of the display area; a gate electrode disposed on the first substrate and including a first-layer gate electrode and a second-layer gate electrode disposed on the first-layer gate electrode; a pixel electrode disposed on the same layer as the first-layer gate electrode; a source electrode and a drain electrode disposed on the gate electrode to be spaced from each other; and a contact connecting the drain electrode and the pixel electrode and including a first-layer contact, which is disposed on the same layer as the pixel electrode, and a second-layer contact, which is disposed on the first-layer contact.

The invention discloses a circuit board module. The circuit board module comprises a circuit board, and a first electronic component, a second electronic component and a third electronic component that are arranged on the circuit board, and an electromagnetic shielding cover; the first electronic component is covered by the electromagnetic shielding cover; the second electronic component and the third electronic component are positioned on the two sides of the first electronic component respectively and are electrically connected through wires. The invention also discloses a communication device. According to the circuit board module, the printed circuit wiring on the circuit board is reduced, the wiring area on the circuit board is reduced, the existing wiring space is fully utilized, and the cost of the circuit board is reduced without influencing the PCB appearance and the electromagnetic shielding property of electromagnetic sensitive electronic components.

The invention provides a shifting register and a gate drive circuit using the shifting register. The shifting register comprises a plurality of repeat units, wherein each repeat unit comprises at least five grades of shifting register units, the last grade of shifting register units is structurally different from the preceding grades of shifting register units, the preceding grades of shifting register units are structurally the same and all comprise four switch units, and the last grade of shifting register units has a reset function and comprises five switch units. The shifting register is stable in outputting, simple in structure, and low in power consumption, so that the gate drive circuit using the shifting register is small in size.

The present invention relates to a sensing structure of touch panel, which comprises a plurality of first electrode groups are located on a first side of a substrate. The bottom of each first electrode is located on the first side and extends towards a second side. A plurality of extended electrode groups are connected to the plurality of first electrode groups, respectively. The bottom of each extended electrode is located on the second side and extends towards the first side. The plurality of second electrode groups are located on the substrate. A first sub-electrode of each second electrode is interleaved with and insulated electrically from each extended electrode. The plurality of third electrode groups are located on the substrate and have a plurality of third electrodes. A first sub-electrode of the third electrode is interleaved with and insulated electrically from the second sub-electrode of the second electrode.

Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.

A welding wire for use in electric arc welding and method of making same, wherein the wire has an effective outer diameter and comprises a length of solid metal formed into a series of distinct segments each having a selected volume and having an indented and non-indented region with the cross sectional area of the solid metal at said non-indented region being greater than the cross sectional area of the solid metal at the indented region.

A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

The invention relates to a processing method of plating wire distribution of IC packing substrate, including: a. arranging plating wires between wire patterns in packing substrate units to make all the wires of the wire patterns connect mutually by plating wires, where the plating wires or wire patterns connect with metal power supply layers in packing substrates; b. making plating treatment on the packing substrates and eliminating the plating wires by chemically etching process. The invention public plating wires between wire patterns in the packing substrates units, where the plating public wires are thinner than the wire patterns and narrower than the narrowest wire pattern, and eliminates the public wires by etching process, can make the shape change of the wire patterns minimum by controlling etching process conditions, thus beneficial to the improvement of electric performance of the substrate, assuring the integrity of signals and able to reduce wiring area, especially applied to make high-frequency high-speed IC packing substrates.