192results about How to "Reduced wiring area" patented technology

The invention discloses a touch drive circuit, an optical embedded touch screen and a display device, wherein the touch drive circuit comprises a light sensitive submodule, a data writing submodule, a drive submodule and a control submodule. Under the control of a scanning signal terminal, the data writing submodule transmits a scanning signal of the scanning signal terminal to the drive submodule; when the drive submodule is controlled to be opened by the scanning signal, the drive submodule outputs a touch sensing signal to the control submodule, and the touch sensing signal is reduced with increasing of light intensity of the light sensitive submodule; and under the control of a control signal terminal, the control submodule inputs the touch sensing signal to a touch signal reading terminal, so that the touch function is realized. Compared with a drive circuit of a conventional optical embedded touch screen, the control submodule is used for controlling the drive submodule to transmit the touch sensing signal to the touch signal reading terminal, and when the touch signal reading terminal of each level of drive circuits is connected with the same touch signal reading wire, signals output by different levels of drive circuits can be prevented from mutual crosstalk.

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

This present invention provides a liquid-crystal panel that presents a high-density wiring while maintaining reliability of the wiring. Odd-numbered scanning lines are connected to a first wiring group while even-numbered scanning lines are connected to a second wiring group. Each of the scanning lines is supplied with a scanning signal the polarity of which is inverted every horizontal scanning period. Among wirings forming the first wiring group and the second wiring group, a line-to-line voltage between any adjacent wirings becomes zero volt for a majority of the time. Accordingly, degradation of the wirings due to electrolytic corrosion is controlled even if the spacing between the wirings is narrowed.

A system and method for correcting wiring congestion in a placed and partially or fully globally-routed VLSI chip design while avoiding adding new timing or electrical violations or other design constraints. Globally-congested areas are identified along with determining terminated and non-terminated wires in the congested areas. The process includes optimizing the identified congestion areas, incrementally rerouting affected nets, testing the resultant design legality and congestion metrics, and committing or reversing the optimizations and reroutings. The optimizations further includes the movement of logic cells and decomposition, recomposition or any other modification of logic cell structures (possibly combined with cell movement) to move terminated wires to less congested grid edges, rearrangement of commutative connections within or between cells, or addition of buffers to cause reroutes of feedthrough wires.

A welding wire for use in electric arc welding and method of making same, wherein the wire has an effective outer diameter and comprises a length of solid metal formed into a series of distinct segments each having a selected volume and having a narrow region and non-narrow region with the cross sectional area of the solid metal at said non-narrow region being greater than the cross sectional area of the solid metal at the narrow region.

A semiconductor package having an impedance matching device is disclosed, which is especially applicable to conventional system-in-package structures and system packaging design with high-density I / O design. The impedance matching device achieves impedance matching between a semiconductor chip and a signal transmission wiring on the substrate or between different systems integrated in the semiconductor package by employment of a vertical conductive line or combination of a vertical conductive line and a stub transmission line. The vertical conductive line is electrically connected with the signal transmission wiring on the substrate at one end thereof, and the stub transmission line may be further connected to the other end of the vertical conductive line. This impedance matching device helps to effectively reduce the wiring area of an impedance matching network of the semiconductor package and enhance the flexibility and interchangeability in layout of the wiring.

The invention provides a shifting register and a gate drive circuit using the shifting register. The shifting register comprises a plurality of repeat units, wherein each repeat unit comprises at least five grades of shifting register units, the last grade of shifting register units is structurally different from the preceding grades of shifting register units, the preceding grades of shifting register units are structurally the same and all comprise four switch units, and the last grade of shifting register units has a reset function and comprises five switch units. The shifting register is stable in outputting, simple in structure, and low in power consumption, so that the gate drive circuit using the shifting register is small in size.

A receptacle structure includes a housing structure, a terminal insulating board, a first terminal and a second terminal. The housing structure is configured to be mounted on a printed wiring board and to accommodate a plug. The terminal insulating board includes a top face and a bottom face that is opposite to the top face. The terminal insulating board is disposed inside the housing structure with the bottom face facing towards the printed wiring board. The first terminal is connected to the printed wiring board via the first rear connection part and to the terminal insulating board. The second terminal is connected to the printed wiring board via the first front connection part and to the terminal insulating board. The first front connection part has a width narrower than the first rear connection part and is connected to the printed wiring board away from the first rear connection part.

A welding wire for use in electric arc welding and method of making same, wherein the wire has an effective outer diameter and comprises a length of solid metal formed into a series of distinct segments each having a selected volume and having an indented and non-indented region with the cross sectional area of the solid metal at said non-indented region being greater than the cross sectional area of the solid metal at the indented region.

A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.