98results about How to "Reduce time difference" patented technology

For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

To set trigger conditions correctly in pneumatic mode, a ventilator is controlled to obtain a measurement value of a bioelectric signal representative of the patient's breathing function, determine, based on the bioelectric signal, at least one point in time at which the patient starts inhalation, obtain a measurement value to be used for triggering an inspiration phase in the ventilator during the at least one point in time, determine a trigger condition for the inspiration phase on the basis of the measurement value, and use the trigger condition for initiating inspiration when ventilating the patient in support mode.

The present invention provides a camera and a camera zoom control method that can reduce power consumption at the time of zooming and shorten the time difference between the timing of a photographing instruction and the timing of actual photographing. Until a release button is operated, the optical zoom magnifying power of a lens is controlled to become a zoom magnifying power corresponding to an operation with respect to a zoom switch, and when the release button has been operated, the optical zoom magnifying power of the lens is controlled to become the zoom magnifying power corresponding to the operation with respect to the zoom switch.

A twinax cable includes at least a pair of core wires, each of which includes a conductor and an insulator covering an outer periphery of the conductor. The insulator includes an inner insulator covering the outer periphery of the conductor and an outer insulator covering an outer periphery of the inner insulator. The inner insulator is formed by a non-colored compressed insulator. The outer insulator is formed by a colored compressed insulator. A thickness of the outer insulator is formed thinner than a thickness of the inner insulator. The outer insulators of the pair of core wires are formed to have hues that are set respectively differently.

In an embodiment, the access node includes first and second transceiver units for initializing first and second communication channels, respectively, over first and second communication lines, respectively. The initialization of the first and second communication channels respectively including first and second handshake phases wherein peer transceiver units exchange capabilities and select (i) a common mode of operation, (ii) first and second crosstalk channel acquisition phases from the first and second communication lines, and (iii) first and second generic initialization phases. The access node further includes a line initialization controller configured to stretch the execution of the first handshake phase with respect to the execution of the second handshake phase so as to shorten a time difference between respective entries into the first and second crosstalk channel acquisition phases.

A transfer circuit 25 includes two sets of an input circuit 52A and an output circuit 53B, which allows bidirectional transfer. The input circuit 52A decomposes external input data signals DI11A and DI12A to signals on lines L11 to L14 in synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuit 53B composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DO11B and DO12B. Signals on either the lines L11 to L14 or L21 to L24 are selected by a multiplexer 57 to provide to a main body circuit.

A DLL circuit comprising: delay circuits which output first and second delayed clock signals obtained by delaying the reference clock signal by a delay times selected according to control signals; an interpolation circuit which interpolates a phase difference between the delayed clock signals to output an internal clock signal; an output circuit which generates a predetermined signal; a dummy output circuit which has the same transmission characteristics as the output circuit and outputs a feedback clock signal having the same phase as the predetermined signal; a phase comparison circuit which compares phases of the reference clock signal and the feedback clock signal; delay control circuits which controls the control signals in a direction where both phases are equal; wherein the delay time of the second delayed clock signal is larger than the first delayed clock signal by an amount equivalent to one cycle of the reference clock signal.

A magnetic-sensor controller includes an input section, a perpendicular-bisector calculation section, a storage section, and a setting section. The input section successively inputs a plurality of magnetic data sets successively output from a three-dimensional magnetic sensor. Each magnetic data includes three components. The perpendicular-bisector calculation section calculates, for each pair of two of the magnetic data sets, a perpendicular bisector of two points corresponding to the two magnetic data sets. The storage section stores a plurality of perpendicular bisectors. The setting section statistically approximates, by a single point, a region where the plurality of perpendicular bisectors stored in the storage section meet, and sets an offset of the magnetic data set on the basis of the single point. The magnetic-sensor controller enables accurate setting of an offset even when the magnetic field strength changes.

First memory chips each have a memory cell as storage means for storing data and do not have a redundant memory cell as redundant storage means for repairing an erroneous bit in the memory cell. Furthermore, a logic minimal in degree is solely provided for operation on a control logic of a second memory chip. The second memory chip has a control logic for effecting memory control of the memory cells, the redundant memory cells, etc. and a redundant memory cell for repairing an error bit of the first memory chips. The memory device is structured by stacking the first and second memory chips.

A time keeping system having a first time module operable to keep a first time, a second time module operable to keep a second time, and a control module operatively coupled to the first time module and to the second time module. The control module adjusts the first time in response to information stored in the control module and adjusts the second time to reduce a time difference between the first time and the second time.

Apparatuses and methods for decoding a spreading code-encoded signal. The decoder decodes a spreading code-encoded signal by performing a synchronization search to determine a synchronization point. The synchronization point defines a time delay for aligning a spreading code, which was used to generate the spreading code-encoded signal, with the spreading code-encoded signal. The synchronization search includes obtaining candidate results, where each candidate result is a decoding attempt that applies a time delay for aligning the spreading code with the spreading code-encoded signal. The synchronization search also includes determining the synchronization point by identifying the time delay corresponding to the candidate result that is associated with a power measurement that satisfies a synchronization search criterion. A decoder code synchronization is performed to align the spreading code with the spreading code-encoded signal, using the synchronization point. The spreading code-encoded signal is decoded using the aligned spreading code.

The invention discloses a plate spring double-headed synchronous eye coiling production line and head cutting, eye coiling and shaping units thereof. The production line is sequentially provided with a feeding unit, a heating unit, the head cutting unit, the eye coiling unit, the shaping unit and a product integrated packaging unit from front to back. A mechanical arm guiding track bracket which extends front and back is arranged between the feeding unit and the product integrated packaging unit, and the mechanical arm guiding track bracket is provided with a mechanical arm so that a plate spring can be transferred between all the units. The number of electromagnetic heating furnaces, the number of head cutting machines, the number of eye coiling machines and the number of shapers are all two, and the electromagnetic heating furnaces, the head cutting machines, the eye coiling machines and the shapers are all symmetrically arranged relative to the left-right center base line of the production line. The plate spring can be positioned when the two ends of the plate spring are heated, the transferring time difference to the head cutting process is shortened, the thermoplasticity of the plate spring in the head cutting process is guaranteed, the two ends can be cut synchronously in the head cutting process, and thus efficiency is high. In the eye coiling process, the feed machining method of the eye coiling machines is adopted, double-headed synchronous eye coiling is realized, eye machining efficiency is greatly improved, and the quality of obtained coiled eyes is obviously improved as well. Double-headed synchronous shaping is conducted, and hence the depth of parallelism of the coiled eyes of the plate spring can be better improved.

A local clock signal generation system is disclosed including multiple local clock buffers each receiving a global clock signal and producing a version of one or more local clock signals derived from the global clock signal. Each local clock buffer includes an input section and an output section. The input sections are substantially identical such that timing differences between the versions of the one or more local clock signals are reduced. An electronic circuit is described including the local clock signal generation system and a latch (e.g., a master latch of a flip-flop). A local clock buffer produces a gating signal and a local clock signal received by the latch. When the gating signal is a certain logic value, the local clock signal is a steady logic value, and the latch produces an input data signal as an output signal. An integrated circuit including the electronic circuit is disclosed.

An apparatus includes a drop unit, a transfer unit and a position adjusting unit. The drop unit drops droplets of an organic material. The transfer unit transfers the drop unit along a first direction. The position adjusting unit is interposed between the drop unit and the transfer unit to adjust a position of the drop unit. Therefore, the apparatus of dropping the organic material has a small size and may drop droplets of the organic material onto an accurate position. Furthermore, the transfer unit moves the drop unit quickly, and the position adjusting unit adjusts the position of the drop unit accurately. Therefore, a time difference for drying the organic material injected into a cavity is reduced.

An uninterruptible power supply is having a battery, a power inverter circuit for inverting the electrical power of the battery, and a voltage control circuit. The voltage control circuit controls the power inverter circuit, so that the output voltage of the power inverter circuit is maintained at a standby voltage lower than a rated voltage under the condition of a power failure detection signal being not output from an external power supply and the output voltage of the power inverter circuit equals the rated voltage under the condition of the power failure detection signal being output from the external power supply.