Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure

Abstract

The invention relates to a processing method of plating wire distribution of IC packing substrate, including: a. arranging plating wires between wire patterns in packing substrate units to make all the wires of the wire patterns connect mutually by plating wires, where the plating wires or wire patterns connect with metal power supply layers in packing substrates; b. making plating treatment on the packing substrates and eliminating the plating wires by chemically etching process. The invention public plating wires between wire patterns in the packing substrates units, where the plating public wires are thinner than the wire patterns and narrower than the narrowest wire pattern, and eliminates the public wires by etching process, can make the shape change of the wire patterns minimum by controlling etching process conditions, thus beneficial to the improvement of electric performance of the substrate, assuring the integrity of signals and able to reduce wiring area, especially applied to make high-frequency high-speed IC packing substrates.

Description

technical field [0001] The invention relates to a semiconductor circuit packaging substrate manufacturing technology, in particular to a method for laying out electroplating lead wires on an integrated circuit packaging substrate, and an electroplating lead structure on the substrate. Background technique [0002] With the miniaturization and thinning of the development of integrated circuits, the requirements for integrated circuit packaging are also increasing, and the requirements for packaging substrates are more light, thin, short, and small to ensure good electrical performance. In order to meet the above requirements, a high wiring density is necessary, and the structure of the plating leads on the outer layer of the packaging substrate has a great influence on the wiring density and the electrical performance after packaging. [0003] At present, the following two methods are usually used for the layout of the common connection lines for the plating of printed semico...

AI Technical Summary

Problems solved by technology

This kind of remaining electroplating lead causes signal loss and interference to the high-speed signal line on the high-frequency and high-speed packaging substrate, affecting the integrity of the signal

At the same time, it increases the difficulty of wiring, and even in the case of very high-density wiring, it is impossible to realize the arrangement of plating leads

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