75results about How to "Small line width" patented technology

A touch panel control device may be provided that includes: a touch panel which generates at least one touch signal in response to a touch of an object; a displayer; and a controller which performs a first touch action mode in which the change of the touch position of the object is displayed on the displayer by a line in response to the object which has touched the touch panel, and performs a second touch action mode in which, in response to the position change of the object which corresponds to the position of the line displayed on the displayer, it is to carry out at least one of the removal of at least a portion of the line displayed on the displayer and the change of the color coordinate of the line. Also, a method for controlling the touch panel may be also provided.

A chip-component structure includes an interposer on which a multilayer capacitor is mounted. The interposer includes component connecting electrodes, external connection electrodes, side electrodes, and in-hole electrodes. The component connecting electrodes and the external connection electrodes are electrically connected by the side electrodes and the in-hole electrodes. Outer electrodes of the capacitor are joined to the component connecting electrodes.

The present invention pertains to a method of fabricating a trench capacitor having increased capacitance. To tackle a difficult problem of etching deeper trenches having very high aspect ratio, an epitaxial silicon growth process is employed in the fabrication of next-generation trench DRAM devices. A large-capacitance trench capacitor is first fabricated in the silicon substrate. An epitaxial silicon layer is then grown on the silicon substrate. Active areas, shallow trench isolation regions, and gate conductors are formed on/in the epitaxial silicon layer.

A p-type MIS transistor includes a first gate insulating film formed on a first active region; and a first fully silicided gate pattern that is obtained by fully siliciding a silicon film, is formed to extend over the first active region with the first gate insulating film sandwiched therebetween, and includes a first fully silicided gate electrode provided on the first active region and a first fully silicided gate line provided on the isolation region. The first fully silicided gate pattern includes, along a gate width direction, a portion having a first thickness and including the first fully silicided gate electrode and portions each having a second thickness larger than the first thickness and respectively disposed on both sides of the portion having the first thickness.

A touch panel including a first and a second substrates, a first and a second sensing electrode layers, plural first lines, plural second lines, a conductive material layer and a shielding layer is provided. The first and the second sensing electrode layers are respectively disposed on the first and the second substrates and located in a sensing region. The first and the second lines are disposed on the first substrate and located in a periphery region. The first lines connect to the first sensing electrode layer. The optical adhesive layer encapsulates the first and the second sensing electrode layers and the first and the second lines. The optical adhesive layer has an opening. The conductive material layer is disposed inside the opening. The second lines connect to the second sensing electrode layer via the conductive material layer. The shielding layer is located above the first and the second lines.

When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.

There is disclosed a method for applying a first metal on a substrate, which method comprises the steps a) producing polymers on the surface of said substrate, said polymers comprising carboxylic groups and adsorbed ions of at least one second metal, said ions being adsorbed at a pH above 7, b) reducing said ions to the second metal and c) depositing said first metal on the reduced ions of said second metal. The invention further comprises objects manufactured according to the method. Advantages of the present invention include improved adhesion of the metal coating, possibility to coat many difficult materials. The process is suitable for large-scale and continuous production and it will reduce the waste of metal. Circuits manufactured according to the invention display improved signal integrity. Also there is the possibility to manufacture circuits which are built up sequentially with several layers of conductors in distinct patterns. It is also possible to manufacture of circuits with a very small line width.

The printed circuit board includes the via formed with the electroplating layer unlike a conventional via formed with an electroless plating layer and an electroplating layer and having a cylindrical shape, and thus exhibits good interlayer electrical connection and high reliability of physical contact upon thermal stress caused by the variance in physical properties of material depending on changes in temperature. The via has no upper land, and thus a fine circuit pattern of the circuit layer can be formed on the via.

There is disclosed a semiconductor device comprising a plurality of inter-level dielectric films which are stacked and provided in plural layers above a substrate, at least one first conductor which is provided in at least one inter-level dielectric film of the stacked inter-level dielectric films, and a plurality of second conductors which are provided in the inter-level dielectric film in which the first conductor is provided and which are connected to the lower surface of the first conductor and which are extended along the downward direction from the first conductor and further extended along a first direction and a second direction perpendicular to the first direction in such a manner as to be spaced apart from each other to form a lattice shape.

A method for producing an electromagnetic-shielding transparent window member including a transparent film and a patterned conductor disposed thereon includes the steps of applying a resin coating material containing a catalyst for electroless plating to the transparent film to form a patterned resin having the same pattern as the patterned conductor to be formed; and depositing a conductive material only on the patterned resin by electroless plating to form the patterned conductor.

An array substrate, a display panel, and a display device are provided. The array substrate includes a display region and a non-display region surrounding the display region. The array substrate also includes a plurality of gate lines. The plurality of gate lines include a plurality of regular gate lines and at least one irregular gate line. The plurality of regular gate lines are disposed in the display region and extended along a first direction. The at least one irregular gate line includes at least one first trace portion and a second trace portion electrically connected to each other. The at least one first trace portion has a same line width as a regular gate line of the plurality of regular gate lines, and the second trace portion has a line width smaller than the at least one first trace portion.

There is disclosed a chemically-amplified positive resist composition comprising, as main components, (A) a base polymer, which contains one or more kinds of a monomer unit represented by the following general formula (1) and the like, and is an alkali-insoluble polymer whose hydroxyl group is partly protected by an acetal group while alkali-soluble when deprotected by an acid catalyst, (B) a sulfonium salt containing a sulfonate anion, (C) a basic component, and (D) an organic solvent. In a lithography technology by a photo resist, an extremely high temporal stability is necessary. In addition, it must give a good pattern profile not dependent on a substrate and have a high resolution power. There can be provided a chemically-amplified positive resist composition which can solve these problems simultaneously, a resist patterning process using the same, and a method for producing a photo mask blank.

A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.

Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask. The trench is substantially narrower than the second opening and has a sidewall that has a second inclination angle that is substantially larger than the first inclination angle.

The invention provides a forming method of a pattern, comprising the steps as follows: firstly, a material layer is provided; a patterned hard mask layer is formed on the material layer; subsequently, a clearance wall is respectively formed on the side wall of the patterned hard mask layer; subsequently, the patterned hard mask layer is removed and an opening is formed between the two adjacent clearance walls; subsequently, the clearance wall is used as the mask so as to remove a part of material layer, thus forming a patterned material layer.

A pixel array substrate including a substrate, data lines, gate lines, pixels, and transfer lines is provided. The data lines are disposed on the substrate and arranged in a first direction. The gate lines are disposed on the substrate and arranged in a second direction interlaced with the first direction. The pixels are disposed on the substrate, each of which includes an active device electrically connected to one of the data lines and one of the gate lines and a pixel electrode electrically connected to the active device. The transfer lines are arranged in the first direction and electrically connected to the gate lines, respectively. The pixels include first pixels. In a top view of the pixel array substrate, at least one of the pixel electrodes of the first pixels is partially overlapped with one of the transfer lines. A driving method of a pixel array substrate is also provided.

A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.