87results about How to "Lower ESL" patented technology

In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

A multilayered chip capacitor including a capacitor main body including a plurality of dielectric layers, which are laminated; at least one pair of first and second internal electrodes, each of which is formed on the corresponding one of the plural dielectric layers and includes at least one lead extended to one end of the corresponding dielectric layer; a plurality of external terminals formed on the outer surface of the capacitor main body, and respectively connected to the first and second internal electrodes through the leads; and at least one opened region, formed through the inner area of each of the first and second internal electrodes, for branching the flow of current so as to increase the offset quantity of parasitic inductances between the first and second internal electrodes.

A multilayer capacitor 10 comprising a dielectric body 12 having an approximately rectangular parallelepiped shape formed by alternately stacking a plurality of dielectric layer 12a, a first conductor layer 21, a second conductor layer 22, a first terminal electrode 31 and a second terminal electrode 32 formed on a first side face 12A of side faces 12 of the dielectric body in parallel to a stacking direction Z. The first conductor layer 21 comprises a first lead portion 21L connected to the first terminal electrode 31, the second conductor layer 22 comprises a second lead portion 22L connected to the second terminal electrode 32. Between a length “a” of the first lead portion 21L and the second lead portion 22L in vertical direction to the stacking direction Z, a length “b” of conductor layers positioned at both ends of the dielectric body 12 in the stacking direction, a space length “c” of the first side face 12A and the first conductor layer 21, a total number of the conductor layers 22, 22, (a+c)/(b×n)≦0.035 is consisted.

A monolithic capacitor includes a main capacitor unit having first capacitor portions and a second capacitor portion arranged in a direction of lamination, with the first capacitor portion located towards at least one end in the direction of lamination, so that the first capacitor portion is located closer to a mounting surface than the second capacitor portion. The number of pairs of third and fourth lead-out portions for third and fourth internal electrodes in the second capacitor portion is less than the number of pairs of first and second lead-out portions for first and second internal electrodes in the first capacitor portion, so that the first capacitor portion contributes to decreasing ESL while the second capacitor portion contributes to increasing ESR.

A multilayer capacitor includes: a dielectric element; two kinds of terminal internal conductors and two kinds of connecting internal conductors both disposed in the dielectric element; two kinds of terminal electrodes; and two kinds of external electrodes, wherein: the terminal internal conductor of one kind has a first terminal-side leadout portion led out to one face of the dielectric element and a first external-side leadout portion led out to the other face, and the terminal internal conductor of the other kind has a second terminal-side leadout portion led out to the one face and a second external-side leadout portion led out to the other face; the connecting internal conductor of one kind has a third external-side leadout portion led out to the other face, and the connecting internal conductor of the other kind has a fourth external-side leadout portion led out to the other face; the terminal electrode of one kind is connected to the first terminal-side leadout portion, and the terminal electrode of the other kind is connected to the second terminal-side leadout portion; and the external electrode of one kind is connected to the first external-side leadout portion and the third external-side leadout portion, and the external electrode of the other kind is connected to the second external-side leadout portion and the fourth external-side leadout portion. Therefore, a multilayer capacitor easily realizing a higher capacity and reduced ESL is obtained.

A chip-component structure includes an interposer on which a multilayer capacitor is mounted. The interposer includes component connecting electrodes, external connection electrodes, side electrodes, and in-hole electrodes. The component connecting electrodes and the external connection electrodes are electrically connected by the side electrodes and the in-hole electrodes. Outer electrodes of the capacitor are joined to the component connecting electrodes.

A stacked capacitor includes a dielectric member, a plurality of internal electrodes, and a plurality of extraction electrodes. The dielectric member is a stacked member formed of a plurality of sheet-like stacked dielectric layers and has at least one side surface. The internal electrodes fit within the surface area of the dielectric layers and are stacked alternately with the dielectric layers. Further, the internal electrodes have first edges positioned near the side surface. Each extraction electrode has an overlapping portion A overlapping another extraction electrode at the side surface in a direction orthogonal to the mounting direction.

A solid electrolytic capacitor according to this invention includes a capacitor element with a drawn-out anode lead, a conversion substrate mounted with the capacitor element, and a casing resin covering the capacitor element mounted on the conversion substrate. The conversion substrate has, on one surface thereof, a connection pattern composed of an anode portion connected to the anode lead and a cathode portion connected to the body of the capacitor element. The conversion substrate further has, on another surface thereof on the side opposite to the foregoing one surface, a terminal pattern composed of an anode terminal and a cathode terminal connected to the anode portion and the cathode portion through the conversion substrate, respectively. The terminal pattern differs from the connection pattern.

A multilayer capacitor includes: a dielectric element; a plurality of first internal electrodes and a plurality of second internal electrodes alternately arranged in the dielectric element while being separated from each other by dielectric layers; a first outer columnar electrode extending from a surface of the dielectric element to reach the first internal electrode on an outermost layer; a second outer columnar electrode extending from the surface of the dielectric element to reach the second internal electrode on an outermost layer; a first inner columnar electrode connected to all the first internal electrodes and having a cross-sectional area larger than a cross-sectional area of each of the first and second outer columnar electrodes; a second inner columnar electrode connected to all the second internal electrodes and having a cross-sectional area larger than a cross-sectional area of each of the first and second outer columnar electrodes; first external electrodes arranged in an island form on the surface of the dielectric element to be connected to the first outer columnar electrode; and second external electrodes arranged in an island form on the surface of the dielectric element to be connected to the second outer columnar electrode. Therefore, it is possible to obtain a multilayer capacitor that realizes reduced total inductance with reduced manufacturing cost.

A solid electrolytic capacitor including capacitor unit having cathode frame coupled to cathode part of capacitor element, and anode frames formed at the opposite sides of capacitor unit sandwiching cathode frame, and coupled to anode part of capacitor element. Flat parts provided at the opposite ends of anode terminals are coupled to anode frames. Flat part provided in the center of cathode terminal is coupled to cathode frame. Capacitor unit is covered with coating resin. The solid electrolytic capacitor has simplified structure and a lower ESL.

Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.

The present invention provides a stacked solid electrolytic capacitor that allows further reducing ESR by increasing the number of stacked layers. The stacked solid electrolytic capacitor according to the present invention is a stacked solid electrolytic capacitor having a plurality of stacked solid electrolytic capacitor elements, and each solid electrolytic capacitor element comprises an anode formed of a valve action metal, an anode section formed on an end of the anode, a dielectric formed on the surface of the valve action metal and comprising an oxide of the valve action metal, and a cathode layer formed on the dielectric. The cathode layers and the anode sections of the solid electrolytic capacitor elements are respectively connected to each other across the plurality of stacked solid electrolytic capacitor elements. A conductive layer extending in the stacking direction is formed on at least part of a side face of an area where the cathode layers of the solid electrolytic capacitor elements are formed.

A solid electrolytic capacitor (A1) includes a first and a second porous sintered bodies (1). Each sintered body (1) is flat, with its thickness being small relative to the width or the length. The first and the second sintered bodies (1) are spaced from each other in the widthwise or lengthwise direction.

A layered capacitor includes a capacitor body that is divided into two first capacitor sections and a second capacitor section. The first capacitor sections are disposed at ends in a layer-stacking direction such that the second capacitor section is interposed between the first capacitor sections in the layer-stacking direction. The resonant frequency of the first capacitor sections is greater than that of the second capacitor section. The total number of third internal electrodes and fourth internal electrodes provided per dielectric layer included in the second capacitor section is less than the total number of first via conductors and second via conductors per dielectric layer included in the first capacitor sections. The ESR per dielectric layer included in the second capacitor section is greater than that per dielectric layer included in the first capacitor sections.