93results about "Feed-through capacitors" patented technology

A feedthrough capacitor not packaged by glass and applicable to an airtight device includes a disk-like ceramic capacitor body (1) of a multilayer laminated structure. A Kovar tube (3) is disposed in an inner hole (2) of the disk-like ceramic capacitor body (1), a conductive pin (4) penetrates through an inner hole (2) of the Kovar tube (3), and the conductive pin (4) and the Kovar tube (3) as well as the Kovar tube (3) and the disk-like ceramic capacitor body (1) are soldered and fixed with gold-tin alloy solder. The distance between the conductive pin (4) and the inner hole (2) of the disk-like ceramic capacitor body (1) is shortened by adding the Kovar tube (3) between the conductive pin (4) and the disk-like ceramic capacitor body (1), so that the amount of the gold-tin alloy solder used in a soldering process is effectively reduced. Because the amount of the gold-tin alloy solder used is reduced, the influence of thermal expansion and contraction of the gold-tin alloy solder on a ceramic capacitor can be greatly relieved, thereby improving the quality of the ceramic capacitor. Moreover, the entire product can be easily cleaned, with no flux left, and dense solder joints are formed to meet specific airtightness requirements.

A connector for a body of a hair care appliance is described. The connector is arranged to connect the body with a power cable, where the body is configured to be held by a user during use of the hair care appliance, and the power cable is used to supply power to the body. The connector includes a capacitor for reducing an amount of electrical noise generated in the body that is transmitted to the power cable. A body comprising the connector and a hair care appliance comprising such a body are also described.

A three-terminal multilayer ceramic capacitor includes end-surface external electrodes on end surfaces, and a side-surface external electrode on at least one side surface. An internal electrode includes an end-surface exposed internal electrode exposed on an end surface and connected to the end-surface external electrode, and a side-surface exposed internal electrode on a side surface and connected to the side-surface external electrode. A lengthwise dimension of the side-surface external electrode satisfies about 0.10 mm<Li<about 0.25 mm, and a total dimension Lall and a total dimension Wall satisfy a relationship of about 0.4 Wall≤Lall≤about 1.0 Wall.

Class Y capacitor (1, 7, 12, 16, 27), which can be connected between a line and ground, comprising a first and a second electric conductor (2, 3), which are separated by a dielectric medium, wherein the first electric conductor (2) is connected to a first leg (4, 8, 9, 13, 18) and the second electric conductor (3) is connected to a second leg (5, 10, 11, 19), wherein the first leg (4, 8, 9, 13, 18) has a larger cross-section than the second leg (5, 10, 11, 19). In addition, an inverter (23) with a class Y capacitor (1, 7, 12, 16, 27) is described.

The utility model discloses a low noise capacitor, and specifically relates to the power capacitor technology field, comprising a capacitor housing, the left and right side walls of the capacitor housing are welded with connecting frames, the two connecting frames are internally provided with filter frames, the filter frames are connected with filter screens, the filter frames are symmetrically welded with two spacing seats, and the spacing seats are arranged on the two spacing seats. A connecting seat is welded on the surface of the capacitor shell, a sliding seat is movably arranged on the surface of the connecting seat in a penetrating mode, one end of the sliding seat is connected with a socket connected with the limiting seat in an inserted mode, and an extrusion spring is connected between the connecting seat and the sliding seat; through the arrangement of the structure, limiting mounting or dismounting cleaning of the filter frame and the filter screen can be rapidly and conveniently achieved, and the practicability of the device is improved.

An interposer device comprising an interposer substrate;a plurality of conducting vias extending through the interposer substrate;a conductor pattern on the interposer substrate, and a nanostructure energy storage device. The nanostructure energy storage device comprises at least a first plurality of conductive nanostructures formed on the interposer substrate;a conduction controlling material embedding each nanostructure in the first plurality of conductive nanostructures;a first electrode connected to each nanostructure in the first plurality of nanostructures; and a second electrode separated from each nanostructure in the first plurality of nanostructures by the conduction controlling material,wherein the first electrode and the second electrode are configured to allow electrical connection of the nanostructure energy storage device to the integrated circuit.

A multilayer ceramic capacitor includes a multilayer body including an inner layer portion in which dielectric layers and internal electrodes are alternately stacked and outer layer portions on both sides of the inner layer portion in a stacking direction, and external electrodes on at least one surface of the multilayer body in a direction intersecting the stacking direction and including main-surface-side folded-back sections and covering a portion of the outer layer portions. A mixture layer of a dielectric and a metal is provided in covered sections of the outer layer portions covered by the main-surface-side folded-back sections.

Systems, devices, and methods discussed herein include wireless midfield transmitters and implantable receiver devices. A midfield transmitter can be configured to provide signals outside of tissue that give rise to propagating signals inside of tissue. The present subject matter includes a protection circuit for a transmitter device, a layered transmitter device, an implantable receiver device, implantation and extraction methods, test and assembly methods, and the like. In an example, a protection circuit includes a first control circuit to receive an RF drive signal and conditionally provide an output signal to an antenna. A second control circuit can generate a control signal based on the antenna output signal and / or information about the RF drive signal. A gain circuit can provide the RF drive signal to the first control circuit. The gain circuit can change an amplitude of the RF drive signal based on the control signal from the second control circuit.

An internally grounded filter feedthrough having a filter capacitor connected to a feedthrough is described. The feedthrough comprises an insulator having an active conductive pathway extending to its device and body fluid sides, and a ground conductive pathway extending part-way through the insulator thickness from the insulator device side. An undercut extending into the insulator sidewall communicates with the ground conductive pathway but does not extend to the insulator device or body fluid sides or to the active conductive pathway. A braze seals the insulator sidewall to the ferrule and extends into the undercut so that the braze contacts the ground conductive pathway. That way, the braze provides a ground electrical path from a capacitor ground via to the ground conductive pathway in the insulator connected to the braze sealed to the ferrule.

A capacitor module is provided between a power storage body and an inverter. The capacitor module comprises a first film capacitor and a second film capacitor that are wound. The first film capacitor includes a first outer peripheral surface. The second film capacitor is connected in parallel to the first film capacitor and includes a second outer peripheral surface opposed to the first outer peripheral surface. A space x between the first outer peripheral surface and the second outer peripheral surface meets a predetermined expression.

To provide a high voltage lead-through capacitor obtained by not using resin sealing material.SOLUTION: A high voltage lead-through capacitor comprises: a capacitor that includes an elementary body 10 in which a through-hole 17 extending in a first direction D1 is formed and a first electrode 11 and a second electrode 12 are arranged opposite to the elementary body; a penetration conductor that is inserted into the through-hole 17, and is electrically connected to a first electrode; a ground metal fitting that is electrically connected to a second electrode 12; and a first case and a second case each having a cylinder shape, and surrounding the circumference of the penetration conductor. The elementary body includes: a first end surface 10a and a second end surface 10b that are opposite to each other in the first direction; a first projected portion 15 that is provided in the first end surface 10a, and has the opened through-hole 17; and a second projected portion 16 that is provided in the second end surface 10b, and has the opened through-hole 17. The first case is attached to the first projected portion. The second case is attached to the projected portion.SELECTED DRAWING: Figure 5

An assembly includes a substrate including a first side and a second side opposite the first side. A first dielectric layer is formed on the first side, and conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening extending at least partially from the first side toward the second side of the substrate. Each of the capacitors includes at least three electrodes. At least one of the plurality of capacitors is coupled to a conductive pad of the first dielectric layer on the first side and to a conductive pad of the second dielectric layer on the second side.

A three-terminal multilayer ceramic capacitor includes a first internal electrode layer including a first facing electrode portion, and first and second extracting electrode portions extending from the first facing electrode portion to a first end surface and a second end surface, respectively, and a second internal electrode layer including a second facing electrode portion facing the first facing electrode portion, and third and fourth extracting electrode portions extending from the second facing electrode portion to first and second side surfaces, respectively, wherein thicknesses of the third and fourth extracting electrode portions in the height direction x>thicknesses of the first and second extracting electrode portions in the height direction x>at least one among thicknesses of the first and second facing electrode portions in the height direction.

Provided is a multilayer ceramic capacitor capable of reducing ESL. A multilayer ceramic capacitor (1) is provided with end surface internal electrodes (20) exposed on both end surfaces (C) of a multilayer body (2) and side surface internal electrodes (50) exposed on both side surfaces (B) of the multilayer body (2). In a laminated ceramic capacitor (1), a straight line extending parallel to the lamination direction (T) and passing through the center of a laminated body (2) in the longitudinal direction (L) and the center of the laminated body (2) in the width direction (W) is set as a reference line (SL), and an end surface internal electrode (20) closest to a first main surface (AA) is set as a first outermost end surface internal electrode (20A). When the distance between the first outermost end surface internal electrode (20A) and the first main surface (AA) on the reference line (SL) is a1 and the distance between one of the ends of the first outermost end surface internal electrode (20A) in the width direction (W) on the first end surface (CA) and the first main surface (AA) is b1, b1lt is set. A1.

The present invention relates to a hermetically sealable capacitive feedthrough (1) for a hybrid module for space applications, the capacitive feedthrough (1) comprising a multilayer ceramic structure having two opposing outer surfaces including a top surface (10) and a bottom surface (20), and metallized outer closure side walls (31, 32, 33, 34) extending vertically between the opposing outer surfaces (10, 20) around the multilayer ceramic structure. The multilayer ceramic structure has, on its upper surface (10), a metallized upper central region (11) designed to receive an input electrical signal to be filtered, a dielectric upper region (12) extending around the metallized upper central region (11), and a metallized upper peripheral region (13) extending around the dielectric upper region (12) until it joins the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric upper region (12) being designed to ensure electrical isolation between the input electrical signal and the electrical ground. and a bottom surface (20) including a metallized bottom central region (21) designed to provide a filtered output electrical signal, a dielectric bottom region (22) extending around the metallized bottom central region (21), and a metallized bottom peripheral region (23) extending around the dielectric bottom region (22) until it joins with the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric bottom region (22) being designed to ensure electrical isolation between the filtered output electrical signal and the electrical ground.The multilayer ceramic structure further includes ceramic layers (41, 42, 43, 44, 45, 46, 47, 48), a first metallization layer (51, 53, 55, 57), and one or more second metallization layers (52, 54, 56) stacked on one another, such that each first metallization layer (51, 53, 55, 57) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the first metallization layer (51, 53, 55, 57), and each / its second metallization layer (52, 54, 56) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the second metallization layer (52, 54, 56). The first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are interposed between the respective ceramic layers (42, 43, 44, 45, 46, 47), and the first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are vertically alternated, whereby each / its second metallization layer (52, 54, 56) has a respective upper first metallization layer (53, 55, 57) disposed above the second metallization layer (52, 54, 56) and a respective lower first metallization layer (51, 53, 55) disposed below the second metallization layer (52, 54, 56), and two ceramic layers (41, 48) are disposed directly below the top surface (10) and directly above the bottom surface (11), respectively. The first metallization layers (51, 53, 55, 57) are bonded to the metallized outer closure sidewalls (31, 32, 33, 34), whereby the first metallization layers (51, 53, 55, 57), the metallized outer closure sidewalls (31, 32, 33, 34), and the metallized top and bottom peripheral regions (13, 23) form an electrical ground structure. Each / its second metallization layers (52, 54, 56) are separated from the metallized outer closure sidewalls (31, 32, 33, 34) by a respective first dielectric gap designed to ensure electrical isolation between the second metallization layers (52, 54, 56) and the electrical ground structure.Each / its second metallization layer (52, 54, 56) is connected to the upper second metallization layer (52, 54, 56) or metallization upper central region (11) through the upper ceramic layer (43, 44, 45, 46, 47, 48) and the respective upper first metallization layer (53, 55, 57) to the second metallization layer (52, 54, 56) and the upper second metallization layer (52, 54, 56) / metallization upper central region (11) and each of the first conductive vias (62, 63, 64) is separated from a respective overlying first metallization layer (53, 55, 57) by a respective second dielectric gap extending around the respective first conductive via (62, 63, 64), thereby forming a respective first capacitor; Each / its second metallization layer (52, 54, 56) is connected to the underlying second metallization layer (52, 54, 56) or metallized bottom central region (21) through the underlying ceramic layer (41, 42, 43, 44, 45, 46) and the respective underlying first metallization layer (51, 53, 55) to the second metallization layer (52, 54, 56) and the underlying second metallization layer (52, 54, 56) / metallized bottom central region (21) The metallization top and bottom central regions (11, 21) and the second metallization layers (52, 54, 56), together with the respective conductive vias (61, 62, 63) and the respective capacitors, form a capacitive feedthrough structure configured to receive an input electrical signal at the metallization top central region (11) and provide a filtered output electrical signal at the metallization bottom central region (21), whereby filtering of the input electrical signal is performed by the capacitors. The metallization top and bottom central regions (11, 21) are planar regions without openings.

The utility model provides a capacitor, comprising a capacitor main body, the capacitor main body comprises a housing having a top plate and a bottom plate, a capacitor core body accommodated in the housing, and a binding post extending through the top plate and electrically connected with the capacitor core body; the barrier unit is arranged below the bottom plate, and the barrier unit is tightly attached to the capacitor main body to form a continuous and gapless interface; wherein the top wall, the side wall and the bottom wall of the blocking unit are closed in the circumferential direction to form a fully-closed hollow structure, a plurality of protruding ribs are arranged on the inner surface of the bottom wall, the ribs and the side wall are arranged at specified intervals, and the ribs intersect with one another to cut the inner surface of the bottom wall into a plurality of sub-areas.

Adaptive DC-DC boost converter arrangement and electronic circuit comprising such an arrangement, e.g. an (audio) amplifier. The arrangement includes a circuit board with a plurality of electronic components mounted thereon, implementing an adaptive DC-DC boost converter circuit (3) and a boost decoupling capacitor (Cbst). The adaptive DC-DC boost converter circuit (3) comprises a DC-DC boost converter (4) having a converter set value input (4i), a boost supply input (4s), and a boost voltage output (4o), and an adaptive DC-DC boost control unit (5) having a control input (5i) and a control output (5o). An acoustical noise suppression filter (6) is present having a filter input (6i) connected to the control output (50) of the adaptive DC-DC boost control unit (5) and a filter output (60) connected to the converter set value input (4i) of the DC-DC boost converter (4).

Multilayer broadband ceramic capacitor (100) having a first end (119) and a second end (121) spaced from the first end (119) in a longitudinal direction (132) perpendicular to a lateral direction (134), wherein the lateral direction (134) and the longitudinal direction (132) are each perpendicular to a Z-direction (136) and wherein the capacitor (100) comprises a top surface (18) and a bottom surface (20) opposite the top surface (18) in the Z-direction (136), wherein the multilayer broadband ceramic capacitor (100) comprises: a monolithic body comprising a multitude of dielectric layers stacked in the Z direction (136); a multitude of active electrodes (106, 108) arranged within the monolithic body; a first outer terminal (118) located along the first end (119), wherein the first outer terminal (118) comprises a bottom part (138) extending along the bottom surface (20) of the capacitor (100); a second outer terminal (120) located along the second end (121), wherein the second outer terminal (120) comprises a bottom part (140) extending along the bottom surface (20) of the capacitor (100), wherein the bottom part (138) of the first outer terminal (118) and the bottom part (140) of the second outer terminal (120) are spaced apart longitudinally (132) by a bottom-outer terminal distance (142); a lower shielding electrode (22) which is arranged within the monolithic body between the plurality of active electrodes (106, 108) and the bottom surface (20) of the capacitor (100), wherein the lower shielding electrode (22) is spaced apart from the bottom surface (20) of the capacitor by a lower shielding-bottom distance (63); where: the lower shield-ground distance (63) is in a range of about 3 µm to about 100 µm; the lower shielding electrode (22, 24) is connected to the first outer terminal (118); the lower shielding electrode (22, 24) has a first longitudinal edge (28) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the lower shielding electrode (22, 24) has a second longitudinal edge (30) which is aligned in the lateral direction (134) and is turned away from the first outer terminal (118); the second longitudinal edge (30) is offset in the longitudinal direction (132) by a shielding electrode offset distance (32) relative to the first longitudinal edge (28); the capacitor has a length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) of the capacitor and the ratio of the capacitor length (21) to the lower outer connection distance (142) is less than approximately 4.

To provide a multilayer ceramic capacitor and a circuit board capable of reducing ESL.SOLUTION: In a multilayer ceramic capacitor, a ceramic element body includes a first internal electrode including an end surface vertical to a first axis, a side surface vertical to a second axis, and a first lead-out part paired with a first electrode body part, and a second internal electrode including a second lead-out part paired with a second electrode body part. A first external electrode is arranged on the end surface and connected to the first lead-out part. The second external electrode is arranged on the side surface and connected to the second lead-out part. At least the first electrode body part or the second electrode body part is arranged apart from an outer edge part and includes a first current limiting part in a shape greater than an aspect ratio of 1.SELECTED DRAWING: Figure 4B

An adaptive DC-DC boost converter arrangement and an electronic circuit including such an arrangement are provided. The arrangement includes a circuit board with a plurality of electronic components mounted thereon, implementing an adaptive DC-DC boost converter circuit and a boost decoupling capacitor. The adaptive DC-DC boost converter circuit comprises a DC-DC boost converter having a converter set value input, a boost supply input, and a boost voltage output, and an adaptive DC-DC boost control unit having a control input and a control output. An acoustical noise suppression filter is present having a filter input connected to the control output of the adaptive DC-DC boost control unit and a filter output connected to the converter set value input of the DC-DC boost converter.

Provided is a multilayer ceramic electronic component that can handle a larger current.　A multilayer ceramic electronic component 100 according to the present invention comprises: a multilayer ceramic capacitor provided with a laminate and at least four or more external electrodes 30, the laminate having a first main surface 12a and a second main surface 12b opposing each other in a lamination direction, a first surface 12c and a second surface 12d opposing each other in a first direction orthogonal to the lamination direction, and a third surface 12e and a fourth surface 12f opposing each other in a second direction orthogonal to the lamination direction and the first direction, and the at least four or more external electrodes 30 being disposed on any of the first surface 12c, the second surface 12d, the third surface 12e, and the fourth surface 12f; and a junction electrode 40 disposed on the first main surface 12a or the second main surface 12b and electrically connecting at least two or more external electrodes of the same potential among the external electrodes 30. The present invention is characterized by satisfying, when the DC resistance of the multilayer ceramic capacitor 10 is denoted by Rdc1 and the DC resistance of the junction electrode 40 is denoted by Rdc3, Rdc1 ≤ Rdc3.

A capacitor component includes a support member; capacitance laminates laminated on one surface of the support member; at least one insulating layer disposed between the capacitance laminates; and a plurality of through structures each penetrating through at least one of the capacitance laminates. Each of the capacitance laminates includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers. One of the plurality of through structures includes a connection conductive pillar connected between first electrode layers of the capacitance laminates. Another of the plurality of through structures includes a first conductive pillar connected to a first electrode layer of one of the capacitance laminates, a dielectric through portion surrounding the first conductive pillar; and a through connection portion surrounding the dielectric through portion and connecting second electrode layers of the capacitance laminates to each other.

A multilayer ceramic capacitor according to the present invention comprises: a laminate that has first and second surfaces that are opposite in the layering direction, third and fourth surfaces that are opposite in a first direction that is orthogonal to the layering direction, and fifth and sixth surfaces that are opposite in a second direction that is orthogonal to the layering direction and the first direction; and an external electrode that is provided on the fifth surface of the laminate. The first external electrode comprises: a base electrode layer that is provided on the fifth surface and is connected to an internal electrode of the laminate; an Sn-Cu diffusion layer that is provided on the base electrode layer and includes tin and copper; an Sn-Ni diffusion layer that is provided outside the Sn-Cu diffusion layer and includes tin and nickel; and an Ni plating layer that is provided on the Sn-Ni diffusion layer and includes nickel as a principal component. There is a gap at the interface between the base electrode layer and the Sn-Cu diffusion layer.

A composite electronic component includes a multilayer ceramic capacitor and a conductor portion. The multilayer ceramic capacitor includes a multilayer body including first, second, third, fourth, fifth, and sixth surfaces, a first external electrode on the first and third surfaces, a second external electrode on the first and fourth surfaces, a third external electrode on the fifth and first surfaces, and a fourth external electrode on the sixth and first surfaces. The conductor portion is electrically connected to the first and second external electrodes. The first external electrode includes a first region on the first surface and a second region on the third surface. The conductor portion includes first and second electrodes respectively connected to the first and second external electrodes by first and second electrically conductive adhesives. Rdc2≤Rdc1 is satisfied. The first electrically conductive adhesive extends from the first region to the second region.

To provide a high-voltage feed-through capacitor that improves reliability.SOLUTION: An element body 10 is formed with through holes 15, 16 respectively to be open at a first main surface and a second main surface opposing each other. A through-conductor 30 includes a portion 32 located inside the through hole 15 and a portion 33 protruding from the second main surface. A through-conductor 40 includes a portion 42 located inside the through hole 16 and a portion 43 protruding from the second main surface. An insulating case 60 is located to surround the element body 10. An insulating cover 50 is located to surround the portions 33, 43. An insulating tube 37 covers the portion 32 and an insulating tube 47 covers the portion 42. A resin 80 fills the inside of the insulating cover 60 so as to reach a space between an inner surface 15a and the insulating tube 37 and a space between an inner surface 16a and the insulating tube 47. The insulating tubes 37, 47 have an electrical resistivity equal to or greater than an electrical resistivity of the resin 80.SELECTED DRAWING: Figure 2

The invention relates to a capacitive element (1) comprising: - a cylindrical casing (10) extending along a longitudinal axis (X); - a core (3) extending along the longitudinal axis (X); - a roll (2), housed inside the casing (10) and formed: o of a first film (20) provided with a first insulating portion (200) extended by a first conductive portion (201), and o of a second film (21) provided with a second insulating portion (210) extended by a second conductive portion (211), the two films (20, 21) being stacked and wound along the longitudinal axis (X) around the core (3) so that the first insulating portion (200) is in contact with the second insulating portion (210) and so that the first conductive portion (201) and the second conductive portion (211) are opposite along the longitudinal axis (X), the first conductive portion (201) forming a first end of the roll (2), the second conductive portion (211) forming a second end of the roll (2), - a first metallized layer (40) formed on an upper surface of the roll (2) at the location of the first end of the roll (2); - a second metallized layer (41) formed on a lower surface of the roll (2) at the location of the second end of the roll (2); - a first electrical connection (60) arranged at least partially on an outer surface of the first metallized layer (40), in contact with the first metallized layer (40); - a second electrical connection (61) arranged at least partially on an outer surface of the second metallized layer (41), in contact with the second metallized layer (41), characterized in that the capacitive element (1) comprises a first electrical connector (50) connected to the first electrical connection (60), and a second electrical connector (51) connected to the second electrical connection (61), the first and second electrical connectors (50, 51) being configured to be directly connected to a power module (8).

A multilayer ceramic capacitor includes an inner-layer portion including first and second inner electrode layers alternately stacked with dielectric layers, a first primary surface, a second primary surface opposite the first primary surface, a first side surface, a second side surface opposite the first side surface, a first end surface, and a second end surface opposite the first end surface, a first outer-layer portion covering the first primary surface in the stacking direction, a second outer-layer portion covering the second primary surface in the stacking direction, and a pair of outer end surface electrodes on the first and second end surfaces. Each of the ceramic dielectrics of the inner-layer portion, the first outer-layer portion, and the second outer-layer portion includes dielectric particles with a void therein. Intragranular void densities in the ceramic dielectric in the inner-layer portion (Ninner), and in the first and second portions (Nouter) satisfy Nouter<Ninner.

A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and / or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and / or may increase the performance of devices and / or integrated circuits in which the capacitive device is included.