59results about "Feed-through capacitors" patented technology

A connector for a body of a hair care appliance is described. The connector is arranged to connect the body with a power cable, where the body is configured to be held by a user during use of the hair care appliance, and the power cable is used to supply power to the body. The connector includes a capacitor for reducing an amount of electrical noise generated in the body that is transmitted to the power cable. A body comprising the connector and a hair care appliance comprising such a body are also described.

A three-terminal multilayer ceramic capacitor includes end-surface external electrodes on end surfaces, and a side-surface external electrode on at least one side surface. An internal electrode includes an end-surface exposed internal electrode exposed on an end surface and connected to the end-surface external electrode, and a side-surface exposed internal electrode on a side surface and connected to the side-surface external electrode. A lengthwise dimension of the side-surface external electrode satisfies about 0.10 mm<Li<about 0.25 mm, and a total dimension Lall and a total dimension Wall satisfy a relationship of about 0.4 Wall≤Lall≤about 1.0 Wall.

The utility model discloses a low noise capacitor, and specifically relates to the power capacitor technology field, comprising a capacitor housing, the left and right side walls of the capacitor housing are welded with connecting frames, the two connecting frames are internally provided with filter frames, the filter frames are connected with filter screens, the filter frames are symmetrically welded with two spacing seats, and the spacing seats are arranged on the two spacing seats. A connecting seat is welded on the surface of the capacitor shell, a sliding seat is movably arranged on the surface of the connecting seat in a penetrating mode, one end of the sliding seat is connected with a socket connected with the limiting seat in an inserted mode, and an extrusion spring is connected between the connecting seat and the sliding seat; through the arrangement of the structure, limiting mounting or dismounting cleaning of the filter frame and the filter screen can be rapidly and conveniently achieved, and the practicability of the device is improved.

An interposer device comprising an interposer substrate;a plurality of conducting vias extending through the interposer substrate;a conductor pattern on the interposer substrate, and a nanostructure energy storage device. The nanostructure energy storage device comprises at least a first plurality of conductive nanostructures formed on the interposer substrate;a conduction controlling material embedding each nanostructure in the first plurality of conductive nanostructures;a first electrode connected to each nanostructure in the first plurality of nanostructures; and a second electrode separated from each nanostructure in the first plurality of nanostructures by the conduction controlling material,wherein the first electrode and the second electrode are configured to allow electrical connection of the nanostructure energy storage device to the integrated circuit.

A multilayer ceramic capacitor includes a multilayer body including an inner layer portion in which dielectric layers and internal electrodes are alternately stacked and outer layer portions on both sides of the inner layer portion in a stacking direction, and external electrodes on at least one surface of the multilayer body in a direction intersecting the stacking direction and including main-surface-side folded-back sections and covering a portion of the outer layer portions. A mixture layer of a dielectric and a metal is provided in covered sections of the outer layer portions covered by the main-surface-side folded-back sections.

An internally grounded filter feedthrough having a filter capacitor connected to a feedthrough is described. The feedthrough comprises an insulator having an active conductive pathway extending to its device and body fluid sides, and a ground conductive pathway extending part-way through the insulator thickness from the insulator device side. An undercut extending into the insulator sidewall communicates with the ground conductive pathway but does not extend to the insulator device or body fluid sides or to the active conductive pathway. A braze seals the insulator sidewall to the ferrule and extends into the undercut so that the braze contacts the ground conductive pathway. That way, the braze provides a ground electrical path from a capacitor ground via to the ground conductive pathway in the insulator connected to the braze sealed to the ferrule.

To provide a high voltage lead-through capacitor obtained by not using resin sealing material.SOLUTION: A high voltage lead-through capacitor comprises: a capacitor that includes an elementary body 10 in which a through-hole 17 extending in a first direction D1 is formed and a first electrode 11 and a second electrode 12 are arranged opposite to the elementary body; a penetration conductor that is inserted into the through-hole 17, and is electrically connected to a first electrode; a ground metal fitting that is electrically connected to a second electrode 12; and a first case and a second case each having a cylinder shape, and surrounding the circumference of the penetration conductor. The elementary body includes: a first end surface 10a and a second end surface 10b that are opposite to each other in the first direction; a first projected portion 15 that is provided in the first end surface 10a, and has the opened through-hole 17; and a second projected portion 16 that is provided in the second end surface 10b, and has the opened through-hole 17. The first case is attached to the first projected portion. The second case is attached to the projected portion.SELECTED DRAWING: Figure 5

An assembly includes a substrate including a first side and a second side opposite the first side. A first dielectric layer is formed on the first side, and conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening extending at least partially from the first side toward the second side of the substrate. Each of the capacitors includes at least three electrodes. At least one of the plurality of capacitors is coupled to a conductive pad of the first dielectric layer on the first side and to a conductive pad of the second dielectric layer on the second side.

A three-terminal multilayer ceramic capacitor includes a first internal electrode layer including a first facing electrode portion, and first and second extracting electrode portions extending from the first facing electrode portion to a first end surface and a second end surface, respectively, and a second internal electrode layer including a second facing electrode portion facing the first facing electrode portion, and third and fourth extracting electrode portions extending from the second facing electrode portion to first and second side surfaces, respectively, wherein thicknesses of the third and fourth extracting electrode portions in the height direction x>thicknesses of the first and second extracting electrode portions in the height direction x>at least one among thicknesses of the first and second facing electrode portions in the height direction.

Provided is a multilayer ceramic capacitor capable of reducing ESL. A multilayer ceramic capacitor (1) is provided with end surface internal electrodes (20) exposed on both end surfaces (C) of a multilayer body (2) and side surface internal electrodes (50) exposed on both side surfaces (B) of the multilayer body (2). In a laminated ceramic capacitor (1), a straight line extending parallel to the lamination direction (T) and passing through the center of a laminated body (2) in the longitudinal direction (L) and the center of the laminated body (2) in the width direction (W) is set as a reference line (SL), and an end surface internal electrode (20) closest to a first main surface (AA) is set as a first outermost end surface internal electrode (20A). When the distance between the first outermost end surface internal electrode (20A) and the first main surface (AA) on the reference line (SL) is a1 and the distance between one of the ends of the first outermost end surface internal electrode (20A) in the width direction (W) on the first end surface (CA) and the first main surface (AA) is b1, b1lt is set. A1.

The present invention relates to a hermetically sealable capacitive feedthrough (1) for a hybrid module for space applications, the capacitive feedthrough (1) comprising a multilayer ceramic structure having two opposing outer surfaces including a top surface (10) and a bottom surface (20), and metallized outer closure side walls (31, 32, 33, 34) extending vertically between the opposing outer surfaces (10, 20) around the multilayer ceramic structure. The multilayer ceramic structure has, on its upper surface (10), a metallized upper central region (11) designed to receive an input electrical signal to be filtered, a dielectric upper region (12) extending around the metallized upper central region (11), and a metallized upper peripheral region (13) extending around the dielectric upper region (12) until it joins the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric upper region (12) being designed to ensure electrical isolation between the input electrical signal and the electrical ground. and a bottom surface (20) including a metallized bottom central region (21) designed to provide a filtered output electrical signal, a dielectric bottom region (22) extending around the metallized bottom central region (21), and a metallized bottom peripheral region (23) extending around the dielectric bottom region (22) until it joins with the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric bottom region (22) being designed to ensure electrical isolation between the filtered output electrical signal and the electrical ground.The multilayer ceramic structure further includes ceramic layers (41, 42, 43, 44, 45, 46, 47, 48), a first metallization layer (51, 53, 55, 57), and one or more second metallization layers (52, 54, 56) stacked on one another, such that each first metallization layer (51, 53, 55, 57) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the first metallization layer (51, 53, 55, 57), and each / its second metallization layer (52, 54, 56) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the second metallization layer (52, 54, 56). The first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are interposed between the respective ceramic layers (42, 43, 44, 45, 46, 47), and the first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are vertically alternated, whereby each / its second metallization layer (52, 54, 56) has a respective upper first metallization layer (53, 55, 57) disposed above the second metallization layer (52, 54, 56) and a respective lower first metallization layer (51, 53, 55) disposed below the second metallization layer (52, 54, 56), and two ceramic layers (41, 48) are disposed directly below the top surface (10) and directly above the bottom surface (11), respectively. The first metallization layers (51, 53, 55, 57) are bonded to the metallized outer closure sidewalls (31, 32, 33, 34), whereby the first metallization layers (51, 53, 55, 57), the metallized outer closure sidewalls (31, 32, 33, 34), and the metallized top and bottom peripheral regions (13, 23) form an electrical ground structure. Each / its second metallization layers (52, 54, 56) are separated from the metallized outer closure sidewalls (31, 32, 33, 34) by a respective first dielectric gap designed to ensure electrical isolation between the second metallization layers (52, 54, 56) and the electrical ground structure.Each / its second metallization layer (52, 54, 56) is connected to the upper second metallization layer (52, 54, 56) or metallization upper central region (11) through the upper ceramic layer (43, 44, 45, 46, 47, 48) and the respective upper first metallization layer (53, 55, 57) to the second metallization layer (52, 54, 56) and the upper second metallization layer (52, 54, 56) / metallization upper central region (11) and each of the first conductive vias (62, 63, 64) is separated from a respective overlying first metallization layer (53, 55, 57) by a respective second dielectric gap extending around the respective first conductive via (62, 63, 64), thereby forming a respective first capacitor; Each / its second metallization layer (52, 54, 56) is connected to the underlying second metallization layer (52, 54, 56) or metallized bottom central region (21) through the underlying ceramic layer (41, 42, 43, 44, 45, 46) and the respective underlying first metallization layer (51, 53, 55) to the second metallization layer (52, 54, 56) and the underlying second metallization layer (52, 54, 56) / metallized bottom central region (21) The metallization top and bottom central regions (11, 21) and the second metallization layers (52, 54, 56), together with the respective conductive vias (61, 62, 63) and the respective capacitors, form a capacitive feedthrough structure configured to receive an input electrical signal at the metallization top central region (11) and provide a filtered output electrical signal at the metallization bottom central region (21), whereby filtering of the input electrical signal is performed by the capacitors. The metallization top and bottom central regions (11, 21) are planar regions without openings.

Adaptive DC-DC boost converter arrangement and electronic circuit comprising such an arrangement, e.g. an (audio) amplifier. The arrangement includes a circuit board with a plurality of electronic components mounted thereon, implementing an adaptive DC-DC boost converter circuit (3) and a boost decoupling capacitor (Cbst). The adaptive DC-DC boost converter circuit (3) comprises a DC-DC boost converter (4) having a converter set value input (4i), a boost supply input (4s), and a boost voltage output (4o), and an adaptive DC-DC boost control unit (5) having a control input (5i) and a control output (5o). An acoustical noise suppression filter (6) is present having a filter input (6i) connected to the control output (50) of the adaptive DC-DC boost control unit (5) and a filter output (60) connected to the converter set value input (4i) of the DC-DC boost converter (4).

To provide a multilayer ceramic capacitor and a circuit board capable of reducing ESL.SOLUTION: In a multilayer ceramic capacitor, a ceramic element body includes a first internal electrode including an end surface vertical to a first axis, a side surface vertical to a second axis, and a first lead-out part paired with a first electrode body part, and a second internal electrode including a second lead-out part paired with a second electrode body part. A first external electrode is arranged on the end surface and connected to the first lead-out part. The second external electrode is arranged on the side surface and connected to the second lead-out part. At least the first electrode body part or the second electrode body part is arranged apart from an outer edge part and includes a first current limiting part in a shape greater than an aspect ratio of 1.SELECTED DRAWING: Figure 4B

Provided is a multilayer ceramic electronic component that can handle a larger current.　A multilayer ceramic electronic component 100 according to the present invention comprises: a multilayer ceramic capacitor provided with a laminate and at least four or more external electrodes 30, the laminate having a first main surface 12a and a second main surface 12b opposing each other in a lamination direction, a first surface 12c and a second surface 12d opposing each other in a first direction orthogonal to the lamination direction, and a third surface 12e and a fourth surface 12f opposing each other in a second direction orthogonal to the lamination direction and the first direction, and the at least four or more external electrodes 30 being disposed on any of the first surface 12c, the second surface 12d, the third surface 12e, and the fourth surface 12f; and a junction electrode 40 disposed on the first main surface 12a or the second main surface 12b and electrically connecting at least two or more external electrodes of the same potential among the external electrodes 30. The present invention is characterized by satisfying, when the DC resistance of the multilayer ceramic capacitor 10 is denoted by Rdc1 and the DC resistance of the junction electrode 40 is denoted by Rdc3, Rdc1 ≤ Rdc3.

A capacitor component includes a support member; capacitance laminates laminated on one surface of the support member; at least one insulating layer disposed between the capacitance laminates; and a plurality of through structures each penetrating through at least one of the capacitance laminates. Each of the capacitance laminates includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers. One of the plurality of through structures includes a connection conductive pillar connected between first electrode layers of the capacitance laminates. Another of the plurality of through structures includes a first conductive pillar connected to a first electrode layer of one of the capacitance laminates, a dielectric through portion surrounding the first conductive pillar; and a through connection portion surrounding the dielectric through portion and connecting second electrode layers of the capacitance laminates to each other.

A multilayer ceramic capacitor according to the present invention comprises: a laminate that has first and second surfaces that are opposite in the layering direction, third and fourth surfaces that are opposite in a first direction that is orthogonal to the layering direction, and fifth and sixth surfaces that are opposite in a second direction that is orthogonal to the layering direction and the first direction; and an external electrode that is provided on the fifth surface of the laminate. The first external electrode comprises: a base electrode layer that is provided on the fifth surface and is connected to an internal electrode of the laminate; an Sn-Cu diffusion layer that is provided on the base electrode layer and includes tin and copper; an Sn-Ni diffusion layer that is provided outside the Sn-Cu diffusion layer and includes tin and nickel; and an Ni plating layer that is provided on the Sn-Ni diffusion layer and includes nickel as a principal component. There is a gap at the interface between the base electrode layer and the Sn-Cu diffusion layer.

The invention relates to a capacitive element (1) comprising: - a cylindrical casing (10) extending along a longitudinal axis (X); - a core (3) extending along the longitudinal axis (X); - a roll (2), housed inside the casing (10) and formed: o of a first film (20) provided with a first insulating portion (200) extended by a first conductive portion (201), and o of a second film (21) provided with a second insulating portion (210) extended by a second conductive portion (211), the two films (20, 21) being stacked and wound along the longitudinal axis (X) around the core (3) so that the first insulating portion (200) is in contact with the second insulating portion (210) and so that the first conductive portion (201) and the second conductive portion (211) are opposite along the longitudinal axis (X), the first conductive portion (201) forming a first end of the roll (2), the second conductive portion (211) forming a second end of the roll (2), - a first metallized layer (40) formed on an upper surface of the roll (2) at the location of the first end of the roll (2); - a second metallized layer (41) formed on a lower surface of the roll (2) at the location of the second end of the roll (2); - a first electrical connection (60) arranged at least partially on an outer surface of the first metallized layer (40), in contact with the first metallized layer (40); - a second electrical connection (61) arranged at least partially on an outer surface of the second metallized layer (41), in contact with the second metallized layer (41), characterized in that the capacitive element (1) comprises a first electrical connector (50) connected to the first electrical connection (60), and a second electrical connector (51) connected to the second electrical connection (61), the first and second electrical connectors (50, 51) being configured to be directly connected to a power module (8).

A multilayer ceramic capacitor (1) according to the present invention comprises a capacitor body (10), a first external electrode (20A), and a second external electrode (20B). A first principal surface (101) is on one side in the layering direction (DS) of the capacitor body (10). The first external electrode (20A) includes a first base electrode layer (21A) and a first surface electrode layer (22A). The first base electrode layer (21A) is provided on the first surface (101) so as to cover a first via conductor (13A). The first surface electrode layer (22A) directly covers the first base electrode layer (21A). The second external electrode (20B) is provided on the first principal surface (101) at a gap from the first external electrode (20A) so as to cover a second via conductor (13B). An outer surface (221A) of the first surface electrode layer (22A) extends away from the first principal surface (101) from an end edge (21AE) of the first base electrode layer (21A) on the first principal surface (101).

A component comprises a substrate comprising a first side and a second side opposite to the first side. A first dielectric layer is formed on the first side, and a plurality of electrically conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and a plurality of electrically conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening that extends at least partially from the first side towards the second side of the substrate. Each of the capacitors comprises at least three electrodes. At least one of the plurality of capacitors is coupled on the first side to an electrically conductive pad of the first dielectric layer and is coupled on the second side to an electrically conductive pad of the second dielectric layer.

The technique described herein targets a modified capacitor (relative to a standard capacitor) in which a first conductor is coupled to a second conductor via a distributed conductive interconnect array through a dielectric layer separating the conductors. The interconnect array facilitates surface current flow between the first and second conductors and determines the capacitor's self-resonant frequency. This conductive interconnect array (or extended area), absent in standard capacitors, allows the capacitor to achieve a higher self-resonant frequency, for example, substantially stable capacitance in the high-frequency radio frequency range, including millimeter-wave frequencies. This further improves the quality factor. The improvements brought about by the technique described herein facilitate the achievement of more optimized surface current densities. Modified capacitors offer advantages in various circuits, such as impedance converters in antenna elements or millimeter-wave frequency phase shifters.

The present invention provides a multilayer ceramic electronic component that suppresses increases in capacitance and DC resistance, while eliminating the need to design the internal structure for each capacitance level. [Solution] The multilayer ceramic electronic component consists of a multilayer ceramic capacitor 10 and a conductor. The multilayer ceramic capacitor 10 has a laminate 12 including a plurality of stacked dielectric layers 14, a first internal electrode layer 16a exposed on the first end face 12e and the second end face 12f of the laminate 12, a second internal electrode layer 16b exposed on the first side surface 12c and the second side surface 12d, a first external electrode 30a and a second external electrode 30b connected to the first internal electrode layer 16a, and a third external electrode 30c and a fourth external electrode 30d connected to the second internal electrode layer 16b. The conductor is electrically connected to the first external electrode 30a and the second external electrode 30b, and the DC resistance RdcA of the conductor is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10.

The invention relates to a capacitive element (1) comprising: a cylindrical housing (10) extending along a longitudinal axis (X); a mandrel (3) extending along said longitudinal axis (X);a reel (2), housed inside said casing (10) and formed of: a first film (20) having a first insulating portion (200) extended by a first conductive portion (201), and a second film (21) having a second insulating portion (210) extended by a second conductive portion (211), the two films (20, 21) being superimposed and wound along said longitudinal axis (X) around said mandrel (3) such that said first insulating portion (200) is in contact with said second insulating portion (210) and that said first conductive portion (201) and said second conductive portion (211) are opposite along said longitudinal axis (X), the first conductive portion (201) forming a first end of said reel (2), the second conductive portion (211) forming a second end of said reel (2), a first metallized layer (40) formed on an upper surface of said bobbin (2) at the location of said first end of said bobbin (2);a second metallized layer (41) formed on a lower surface of said coil (2) at the location of said second end of said coil (2); a first electrical connection (60) provided at least partially on an outer surface of said first metallized layer (40), in contact with said first metallized layer (40); a second electrical connection (61) provided at least partially on an outer surface of said second metallized layer (41), in contact with said second metallized layer (41), characterized in that said capacitive element (1) comprises a first electrical connector (50) connected to said first electrical connection (60), and a second electrical connector (51) connected to said second electrical connection (61), said first and second electrical connectors (50, 51) being configured to be directly connected to a power module (8).

The present disclosure relates to a condenser core configured for surrounding an electrical conductor. The condenser core comprises an insulation material and a plurality of electrically conducting capacitive layers (5) for modifying electrical fields formed by a current flowing in the electrical conductor. At least one of the electrically conducting capacitive layers comprises a first foil (5a) and a second foil (5b). Each of the first and second foils of an outermost capacitive layer is connected with a grounding arrangement (10a, 10b) for grounding the foils.

Provided is a multilayer ceramic electronic component (1) wherein the surface of a multilayer body (2) can be more flattened easily. This multilayer ceramic electronic component (1) is provided with a multilayer body (2) which comprises: first internal electrode layers (10a) that are alternately stacked with a plurality of ceramic layers (4), while being exposed in a first end face (62a); second internal electrode layers (10b) that are alternately stacked with the plurality of ceramic layers (4), while being exposed in a second end face (62b); first level difference layers (5a) which are arranged on the same planes as the second internal electrode layers (10b), while being exposed in the first end face (62a); and second level difference layers (5b) which are arranged on the same planes as the first internal electrode layers (10a), while being exposed in the second end face (62b). The distance between a first level difference layer (5a) and a second internal electrode layer (10b) in the length direction (L) becomes longer as the positions of the first level difference layer (5a) and the second internal electrode layer (10b) are closer to a first main surface (61a); and the distance between a second level difference layer (5b) and a first internal electrode layer (10a) in the length direction (L) becomes longer as the positions of the second level difference layer (5b) and the first internal electrode layer (10a) are closer to the first main surface (61a).

Provided is a multilayer ceramic capacitor that is particularly excellent in terms of moisture resistance. The laminated ceramic capacitor includes an inner layer portion in which a first internal electrode layer and a second internal electrode layer are alternately laminated via dielectric layers formed of a ceramic dielectric, a second main surface which is a surface on the opposite side of the first main surface; a first side surface which is a surface in the width direction orthogonal to the first main surface and the second main surface; a second side surface which is a surface on the opposite side of the first side surface; a first end surface from which the first internal electrode layer is led out, and a second end surface from which the second internal electrode layer is led out, the first end surface being a surface on the opposite side of the first end surface; a first outer layer part which is formed of a ceramic dielectric and covers the first main surface from the lamination direction; a second outer layer part which is formed of a ceramic dielectric and covers the second main surface from the lamination direction; and a pair of outer end surface electrodes provided on the first end surface and the second end surface and connected to the first internal electrode layer and the second internal electrode layer, respectively. The ceramic dielectrics constituting the inner layer section, the first outer layer section, and the second outer layer section each have a plurality of dielectric particles having pores therein. The intra-particle void ratio (Ninner) of the ceramic dielectric in the inner layer portion and the intra-particle void ratio (Nouter) of the ceramic dielectric in the first outer layer portion and the second outer layer portion satisfy formula (1): Nouter lt; and Ninner.

The invention provides a three-terminal multilayer ceramic capacitor capable of improving moisture resistance reliability. In a three-terminal multilayer ceramic capacitor (10), each of a third external electrode (30c) and a fourth external electrode (30d) has a central portion (40) having a thickness of 3 [mu] m or more, and a first convex portion (41a) and a second convex portion (41b) which have a thickness larger than that of the central portion (40) and are positioned closer to a first end surface (12e) and a second end surface (12f) than the central portion (40). A first critical point (45a) and a second critical point (45b) on the first end surface (12e) and the second end surface (12f) side, the thicknesses of the first critical point (45a) and the second critical point (45b) being at least 3 [mu] m from the first external electrode end portion and the second external electrode end portion on the first end surface (12e) and the second end surface (12f) side. A first lead-out end portion (29a) and a second lead-out end portion (29b) of each of the third lead-out electrode portion (28b1) and the fourth lead-out electrode portion (28b2) are located between a first critical point (45a) and a second critical point (45b).

An internally grounded filter feedthrough having a filter capacitor connected to a feedthrough is described. The feedthrough comprises an insulator having an active conductive pathway extending to its device and body fluid sides, and a ground conductive pathway extending part-way through the insulator thickness from the insulator device side. An undercut extending into the insulator sidewall communicates with the ground conductive pathway but does not extend to the insulator device or body fluid sides or to the active conductive pathway. A braze seals the insulator sidewall to the ferrule and extends into the undercut so that the braze contacts the ground conductive pathway. That way, the braze provides a ground electrical path from a capacitor ground via to the ground conductive pathway in the insulator connected to the braze sealed to the ferrule.

Provided is a multilayer ceramic capacitor that can reduce ESL.　A multilayer ceramic capacitor 1 includes: end surface internal electrodes 20 that are exposed at both end surfaces C of a layered body 2; and side surface internal electrodes 50 that are exposed at both side surfaces B. The multilayer ceramic capacitor 1 is configured such that when a straight line that passes through a center part in the length direction L of the layered body 2 and a center part in the width direction W of the layered body 2 and extends parallel to the layering direction T is a reference line SL, the end surface internal electrode 20 that is closest to a first principal surface AA is a first outermost end surface internal electrode 20A, the distance along the reference line SL between the first outermost end surface internal electrode 20A and the first principal surface AA is a1, and the distance along a first end surface CA between one end part in the width direction W of the first outermost end surface internal electrode 20A and the first principal surface AA is b1, b1<a1.