144results about "Feed-through capacitors" patented technology

The technology described herein is directed towards a capacitor with a modified design (relative to standard capacitors), in which a first conductor is coupled to a second conductor via a distributed array of conducting interconnects through a dielectric that separates the conductors. The array of interconnects facilitates electrical surface current flow between the first conductor and the second conductor, and determines the self-resonant frequency of the capacitor. The array (or enlarged area) of conducting interconnects, not present in standard capacitors, results in capacitors with larger self-resonant frequency, e.g., having a substantially stable capacitance over a range of high radio frequencies, including millimeter wave frequencies. This further provides an improved quality factor. The improvements resulting from the technology described herein facilitate more optimal surface current density. The modified capacitor provides benefits in various circuits, e.g., in an impedance or a millimeter wave frequency phase shifter for antenna elements.

A capacitor that includes a substrate having a surface; a lower electrode opposing the surface of the substrate; a dielectric film on the lower electrode; an upper electrode on the dielectric film; a protective layer on the lower electrode, the dielectric film, and the upper electrode, the protective layer defining a through-hole exposing at least one of the lower electrode and the upper electrode; at least one protrusion in the through-hole; and an outer electrode covering the through-hole and the at least one protrusion.

A feedthrough capacitor not packaged by glass and applicable to an airtight device includes a disk-like ceramic capacitor body (1) of a multilayer laminated structure. A Kovar tube (3) is disposed in an inner hole (2) of the disk-like ceramic capacitor body (1), a conductive pin (4) penetrates through an inner hole (2) of the Kovar tube (3), and the conductive pin (4) and the Kovar tube (3) as well as the Kovar tube (3) and the disk-like ceramic capacitor body (1) are soldered and fixed with gold-tin alloy solder. The distance between the conductive pin (4) and the inner hole (2) of the disk-like ceramic capacitor body (1) is shortened by adding the Kovar tube (3) between the conductive pin (4) and the disk-like ceramic capacitor body (1), so that the amount of the gold-tin alloy solder used in a soldering process is effectively reduced. Because the amount of the gold-tin alloy solder used is reduced, the influence of thermal expansion and contraction of the gold-tin alloy solder on a ceramic capacitor can be greatly relieved, thereby improving the quality of the ceramic capacitor. Moreover, the entire product can be easily cleaned, with no flux left, and dense solder joints are formed to meet specific airtightness requirements.

A connector for a body of a hair care appliance is described. The connector is arranged to connect the body with a power cable, where the body is configured to be held by a user during use of the hair care appliance, and the power cable is used to supply power to the body. The connector includes a capacitor for reducing an amount of electrical noise generated in the body that is transmitted to the power cable. A body comprising the connector and a hair care appliance comprising such a body are also described.

A three-terminal multilayer ceramic capacitor includes end-surface external electrodes on end surfaces, and a side-surface external electrode on at least one side surface. An internal electrode includes an end-surface exposed internal electrode exposed on an end surface and connected to the end-surface external electrode, and a side-surface exposed internal electrode on a side surface and connected to the side-surface external electrode. A lengthwise dimension of the side-surface external electrode satisfies about 0.10 mm<Li<about 0.25 mm, and a total dimension Lall and a total dimension Wall satisfy a relationship of about 0.4 Wall≤Lall≤about 1.0 Wall.

Class Y capacitor (1, 7, 12, 16, 27), which can be connected between a line and ground, comprising a first and a second electric conductor (2, 3), which are separated by a dielectric medium, wherein the first electric conductor (2) is connected to a first leg (4, 8, 9, 13, 18) and the second electric conductor (3) is connected to a second leg (5, 10, 11, 19), wherein the first leg (4, 8, 9, 13, 18) has a larger cross-section than the second leg (5, 10, 11, 19). In addition, an inverter (23) with a class Y capacitor (1, 7, 12, 16, 27) is described.

The utility model discloses a low noise capacitor, and specifically relates to the power capacitor technology field, comprising a capacitor housing, the left and right side walls of the capacitor housing are welded with connecting frames, the two connecting frames are internally provided with filter frames, the filter frames are connected with filter screens, the filter frames are symmetrically welded with two spacing seats, and the spacing seats are arranged on the two spacing seats. A connecting seat is welded on the surface of the capacitor shell, a sliding seat is movably arranged on the surface of the connecting seat in a penetrating mode, one end of the sliding seat is connected with a socket connected with the limiting seat in an inserted mode, and an extrusion spring is connected between the connecting seat and the sliding seat; through the arrangement of the structure, limiting mounting or dismounting cleaning of the filter frame and the filter screen can be rapidly and conveniently achieved, and the practicability of the device is improved.

An interposer device comprising an interposer substrate;a plurality of conducting vias extending through the interposer substrate;a conductor pattern on the interposer substrate, and a nanostructure energy storage device. The nanostructure energy storage device comprises at least a first plurality of conductive nanostructures formed on the interposer substrate;a conduction controlling material embedding each nanostructure in the first plurality of conductive nanostructures;a first electrode connected to each nanostructure in the first plurality of nanostructures; and a second electrode separated from each nanostructure in the first plurality of nanostructures by the conduction controlling material,wherein the first electrode and the second electrode are configured to allow electrical connection of the nanostructure energy storage device to the integrated circuit.

A filtered feedthrough comprises an insulator sealed in a ferrule opening. A terminal pin sealed in an insulator via hole has a first end that extends outwardly beyond an insulator device side. A filter capacitor has a square- or rectangularly-shaped dielectric supporting interleaved active and ground electrode plates. A passageway extending through the dielectric has an internal metallization. An external metallization is contacted to opposed longitudinal sides of the dielectric outer surface. The capacitor ground electrode plates extend to the opposed external metallizations. The outwardly extending terminal pin end is connected to the internal metallization in the dielectric passageway which in turn is connected to the active electrode plates. A conductive material connects the capacitor external metallization at one of the longitudinal sides to an oxide-resistant surface on the ferrule while the other external metallization is connected to an oxidized surface of the ferrule.

A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and / or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and / or may increase the performance of devices and / or integrated circuits in which the capacitive device is included.

Systems, devices, and methods discussed herein include wireless midfield transmitters and implantable receiver devices. A midfield transmitter can be configured to provide signals outside of tissue that give rise to propagating signals inside of tissue. The present subject matter includes a protection circuit for a transmitter device, a layered transmitter device, an implantable receiver device, implantation and extraction methods, test and assembly methods, and the like. In an example, a protection circuit includes a first control circuit to receive an RF drive signal and conditionally provide an output signal to an antenna. A second control circuit can generate a control signal based on the antenna output signal and / or information about the RF drive signal. A gain circuit can provide the RF drive signal to the first control circuit. The gain circuit can change an amplitude of the RF drive signal based on the control signal from the second control circuit.

A multilayer ceramic capacitor includes a multilayer body including an inner layer portion in which dielectric layers and internal electrodes are alternately stacked and outer layer portions on both sides of the inner layer portion in a stacking direction, and external electrodes on at least one surface of the multilayer body in a direction intersecting the stacking direction and including main-surface-side folded-back sections and covering a portion of the outer layer portions. A mixture layer of a dielectric and a metal is provided in covered sections of the outer layer portions covered by the main-surface-side folded-back sections.

Systems, devices, and methods discussed herein include wireless midfield transmitters and implantable receiver devices. A midfield transmitter can be configured to provide signals outside of tissue that give rise to propagating signals inside of tissue. The present subject matter includes a protection circuit for a transmitter device, a layered transmitter device, an implantable receiver device, implantation and extraction methods, test and assembly methods, and the like. In an example, a protection circuit includes a first control circuit to receive an RF drive signal and conditionally provide an output signal to an antenna. A second control circuit can generate a control signal based on the antenna output signal and / or information about the RF drive signal. A gain circuit can provide the RF drive signal to the first control circuit. The gain circuit can change an amplitude of the RF drive signal based on the control signal from the second control circuit.

An internally grounded filter feedthrough having a filter capacitor connected to a feedthrough is described. The feedthrough comprises an insulator having an active conductive pathway extending to its device and body fluid sides, and a ground conductive pathway extending part-way through the insulator thickness from the insulator device side. An undercut extending into the insulator sidewall communicates with the ground conductive pathway but does not extend to the insulator device or body fluid sides or to the active conductive pathway. A braze seals the insulator sidewall to the ferrule and extends into the undercut so that the braze contacts the ground conductive pathway. That way, the braze provides a ground electrical path from a capacitor ground via to the ground conductive pathway in the insulator connected to the braze sealed to the ferrule.

A capacitor module is provided between a power storage body and an inverter. The capacitor module comprises a first film capacitor and a second film capacitor that are wound. The first film capacitor includes a first outer peripheral surface. The second film capacitor is connected in parallel to the first film capacitor and includes a second outer peripheral surface opposed to the first outer peripheral surface. A space x between the first outer peripheral surface and the second outer peripheral surface meets a predetermined expression.

Provided is a double-sided copper-clad laminate for forming a capacitor, which, when used as a capacitor, can exhibit excellent characteristics in terms of voltage resistance and peel strength while ensuring high capacitor capacitance. [Solution] A double-sided copper-clad laminate comprising an adhesive layer and copper foil, in that order, on each side of a resin film, the resin film being in a cured state at 25°C, and the copper foil on the side in contact with the adhesive layer has a maximum peak height Sp of 0.05 μm or more and 3.3 μm or less, measured in accordance with ISO 25178.

A semiconductor structure includes a substrate containing first-type deep trenches and second-type deep trenches. The first-type deep trenches and the second-type deep trenches have lengthwise sidewalls that laterally extend along different directions. The semiconductor structure includes a capacitor structure, which includes a layer stack containing at least three metallic electrode layers interlaced with at least two node dielectric layers. Each layer within the layer stack includes a horizontally-extending portion that overlies a top surface of the substrate and vertically-extending portions that protrude downward into a respective one of the first-type deep trenches and second-type deep trenches. The different orientations of the lengthwise directions of the deep trenches reduces deformation of the semiconductor structure. Stress-relief structures may be formed in corner regions of the capacitor structure to provide structural reinforcement.

The present invention provides a multilayer ceramic capacitor which makes it possible to prevent layer separation while also reducing internal stress differences. Provided is a multilayer ceramic capacitor 1 comprising end face exposure internal electrodes 15A and lateral face exposure internal electrodes 15B and comprising first dielectric layers 14A in which the end face exposure internal electrodes 15A are disposed and second dielectric layers 14B in which the lateral face exposure internal electrodes 15B are disposed. In each of the first dielectric layers 14A or the second dielectric layers 14B, an auxiliary internal electrode 16 is disposed toward one surface in which an internal electrode is not disposed, said auxiliary internal electrode 16 being separate from the internal electrode, being exposed at said one surface, and being opposite from a lead-out portion of another internal electrode that is adjacent to said internal electrode in the layering direction. Provided in each auxiliary internal electrode 16 is a through hole 17h which passes therethrough in the layering direction and in which is disposed a dielectric of the same material as the dielectric layer. The dielectric connects a dielectric layer that is on one main surface side and that contacts the auxiliary internal electrode 16 with a dielectric layer that is on another main surface side.

To provide a multilayer ceramic capacitor having ultra-broadband performance.SOLUTION: A multilayer ceramic capacitor 100 includes a monolithic body including a plurality of dielectric layers. A first external terminal 118 is disposed along a first end 119 of the capacitor, and a second external terminal 120 is disposed along a second end 121 thereof. The external terminals have respective bottom portions that extend along a bottom surface 20 of the capacitor. The respective bottom portions of the external terminals are spaced by a bottom external terminal spacing distance 142. Shield electrodes 22, 24 in a bottom shield electrode region 16 are arranged within the monolithic body between a plurality of active electrodes 106, 108 and the bottom surface of the capacitor. The bottom shield electrode is separated from the bottom surface of the capacitor by a distance 63 from the lowest shield to the bottom portion that ranges from about 3 microns to about 10 microns. The ratio of a length 21 of the capacitor to the bottom external terminal spacing distance may be less than about 4.SELECTED DRAWING: Figure 1E

To provide a high voltage lead-through capacitor obtained by not using resin sealing material.SOLUTION: A high voltage lead-through capacitor comprises: a capacitor that includes an elementary body 10 in which a through-hole 17 extending in a first direction D1 is formed and a first electrode 11 and a second electrode 12 are arranged opposite to the elementary body; a penetration conductor that is inserted into the through-hole 17, and is electrically connected to a first electrode; a ground metal fitting that is electrically connected to a second electrode 12; and a first case and a second case each having a cylinder shape, and surrounding the circumference of the penetration conductor. The elementary body includes: a first end surface 10a and a second end surface 10b that are opposite to each other in the first direction; a first projected portion 15 that is provided in the first end surface 10a, and has the opened through-hole 17; and a second projected portion 16 that is provided in the second end surface 10b, and has the opened through-hole 17. The first case is attached to the first projected portion. The second case is attached to the projected portion.SELECTED DRAWING: Figure 5

The present disclosure relates to a condenser core configured for surrounding an electrical conductor. The condenser core includes an insulation material and a plurality of electrically conducting capacitive layers for modifying electrical fields formed by a current flowing in the electrical conductor. At least one of the electrically conducting capacitive layers includes a first foil and a second foil. Each of the first and second foils of an outermost capacitive layer is connected with a grounding arrangement for grounding the foils.

To provide an electrical capacitor that uses polyamideimide as a capacitor material having excellent temperature stability as well as a high or customized dielectric constant.SOLUTION: A capacitor (1) has a single dielectric layer (2) that is free of solid inorganic materials, the dielectric layer (2) includes polyamideimide, and a first electrode (3) disposed directly adjacent to the dielectric layer (2).SELECTED DRAWING: Figure 1

An assembly includes a substrate including a first side and a second side opposite the first side. A first dielectric layer is formed on the first side, and conductive pads extend through the first dielectric layer. A second dielectric layer is formed on the second side, and conductive pads extend through the second dielectric layer. A plurality of capacitors are each formed in an opening extending at least partially from the first side toward the second side of the substrate. Each of the capacitors includes at least three electrodes. At least one of the plurality of capacitors is coupled to a conductive pad of the first dielectric layer on the first side and to a conductive pad of the second dielectric layer on the second side.

An electronic component according to an embodiment including a conductive bonding portion disposed between an external electrode and a frame terminal, and a non-conductive material layer disposed on a band portion of the external electrode. The external electrode may also have a connection portion covering one surface of a body of the electronic component.

An electronic component includes: a first capacitor; and at least one second capacitor that is disposed on the first capacitor along a stacking direction. Each of the first capacitor and the second capacitor includes a dielectric layer and a plurality of internal electrodes spaced apart from each other with the dielectric layer interposed therebetween and disposed in the stacking direction. A distance between the plurality of internal electrodes according to the stacking direction in the first capacitor is greater than a distance between the plurality of internal electrodes according to the stacking direction in the second capacitor.

A three-terminal multilayer ceramic capacitor includes a first internal electrode layer including a first facing electrode portion, and first and second extracting electrode portions extending from the first facing electrode portion to a first end surface and a second end surface, respectively, and a second internal electrode layer including a second facing electrode portion facing the first facing electrode portion, and third and fourth extracting electrode portions extending from the second facing electrode portion to first and second side surfaces, respectively, wherein thicknesses of the third and fourth extracting electrode portions in the height direction x>thicknesses of the first and second extracting electrode portions in the height direction x>at least one among thicknesses of the first and second facing electrode portions in the height direction.

Provided is a multilayer ceramic capacitor capable of reducing ESL. A multilayer ceramic capacitor (1) is provided with end surface internal electrodes (20) exposed on both end surfaces (C) of a multilayer body (2) and side surface internal electrodes (50) exposed on both side surfaces (B) of the multilayer body (2). In a laminated ceramic capacitor (1), a straight line extending parallel to the lamination direction (T) and passing through the center of a laminated body (2) in the longitudinal direction (L) and the center of the laminated body (2) in the width direction (W) is set as a reference line (SL), and an end surface internal electrode (20) closest to a first main surface (AA) is set as a first outermost end surface internal electrode (20A). When the distance between the first outermost end surface internal electrode (20A) and the first main surface (AA) on the reference line (SL) is a1 and the distance between one of the ends of the first outermost end surface internal electrode (20A) in the width direction (W) on the first end surface (CA) and the first main surface (AA) is b1, b1lt is set. A1.

The present invention relates to a hermetically sealable capacitive feedthrough (1) for a hybrid module for space applications, the capacitive feedthrough (1) comprising a multilayer ceramic structure having two opposing outer surfaces including a top surface (10) and a bottom surface (20), and metallized outer closure side walls (31, 32, 33, 34) extending vertically between the opposing outer surfaces (10, 20) around the multilayer ceramic structure. The multilayer ceramic structure has, on its upper surface (10), a metallized upper central region (11) designed to receive an input electrical signal to be filtered, a dielectric upper region (12) extending around the metallized upper central region (11), and a metallized upper peripheral region (13) extending around the dielectric upper region (12) until it joins the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric upper region (12) being designed to ensure electrical isolation between the input electrical signal and the electrical ground. and a bottom surface (20) including a metallized bottom central region (21) designed to provide a filtered output electrical signal, a dielectric bottom region (22) extending around the metallized bottom central region (21), and a metallized bottom peripheral region (23) extending around the dielectric bottom region (22) until it joins with the metallized outer closure sidewalls (31, 32, 33, 34) to act as an electrical ground together with the metallized outer closure sidewalls (31, 32, 33, 34), the dielectric bottom region (22) being designed to ensure electrical isolation between the filtered output electrical signal and the electrical ground.The multilayer ceramic structure further includes ceramic layers (41, 42, 43, 44, 45, 46, 47, 48), a first metallization layer (51, 53, 55, 57), and one or more second metallization layers (52, 54, 56) stacked on one another, such that each first metallization layer (51, 53, 55, 57) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the first metallization layer (51, 53, 55, 57), and each / its second metallization layer (52, 54, 56) is interposed between two respective ceramic layers (41, 42, 43, 44, 45, 46, 47, 48) disposed directly above and below the second metallization layer (52, 54, 56). The first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are interposed between the respective ceramic layers (42, 43, 44, 45, 46, 47), and the first and second metallization layers (51, 52, 53, 54, 55, 56, 57) are vertically alternated, whereby each / its second metallization layer (52, 54, 56) has a respective upper first metallization layer (53, 55, 57) disposed above the second metallization layer (52, 54, 56) and a respective lower first metallization layer (51, 53, 55) disposed below the second metallization layer (52, 54, 56), and two ceramic layers (41, 48) are disposed directly below the top surface (10) and directly above the bottom surface (11), respectively. The first metallization layers (51, 53, 55, 57) are bonded to the metallized outer closure sidewalls (31, 32, 33, 34), whereby the first metallization layers (51, 53, 55, 57), the metallized outer closure sidewalls (31, 32, 33, 34), and the metallized top and bottom peripheral regions (13, 23) form an electrical ground structure. Each / its second metallization layers (52, 54, 56) are separated from the metallized outer closure sidewalls (31, 32, 33, 34) by a respective first dielectric gap designed to ensure electrical isolation between the second metallization layers (52, 54, 56) and the electrical ground structure.Each / its second metallization layer (52, 54, 56) is connected to the upper second metallization layer (52, 54, 56) or metallization upper central region (11) through the upper ceramic layer (43, 44, 45, 46, 47, 48) and the respective upper first metallization layer (53, 55, 57) to the second metallization layer (52, 54, 56) and the upper second metallization layer (52, 54, 56) / metallization upper central region (11) and each of the first conductive vias (62, 63, 64) is separated from a respective overlying first metallization layer (53, 55, 57) by a respective second dielectric gap extending around the respective first conductive via (62, 63, 64), thereby forming a respective first capacitor; Each / its second metallization layer (52, 54, 56) is connected to the underlying second metallization layer (52, 54, 56) or metallized bottom central region (21) through the underlying ceramic layer (41, 42, 43, 44, 45, 46) and the respective underlying first metallization layer (51, 53, 55) to the second metallization layer (52, 54, 56) and the underlying second metallization layer (52, 54, 56) / metallized bottom central region (21) The metallization top and bottom central regions (11, 21) and the second metallization layers (52, 54, 56), together with the respective conductive vias (61, 62, 63) and the respective capacitors, form a capacitive feedthrough structure configured to receive an input electrical signal at the metallization top central region (11) and provide a filtered output electrical signal at the metallization bottom central region (21), whereby filtering of the input electrical signal is performed by the capacitors. The metallization top and bottom central regions (11, 21) are planar regions without openings.

Multilayer broadband ceramic capacitor (100), comprising: a monolithic body comprising a plurality of dielectric layers stacked in a Z-direction (136); a first external terminal (118) disposed along a first end (119) of the capacitor (100), the first external terminal (118) comprising a bottom portion extending along a bottom surface (20) of the capacitor (100); a second external terminal piece (120) arranged along a second end (121) of the capacitor (100) opposite the first end in the longitudinal direction (132), the second external terminal piece (120) comprising a bottom part extending along the bottom surface (20) of the capacitor (100), the bottom part of the first external terminal piece (118) and the bottom part of the second external terminal piece (121) being spaced apart from each other in a longitudinal direction (132) by a lower external terminal distance; a plurality of active electrode layers, wherein a first active electrode layer (102) of the plurality of active electrode layers comprises a first active electrode (106) connected to the first external terminal (118) and a second active electrode connected to the second external terminal (120), the second electrode (108) being coplanar with the first electrode (106), and a second active electrode layer (103) of the plurality of active electrode layers comprising a third active electrode (107) connected to the first external terminal (118) and a fourth active electrode (109) connected to the second external terminal (120), the third electrode (107) being coplanar with the fourth electrode (109), and the first active electrode (106) overlapping the fourth active electrode (109) in the longitudinal direction (132); wherein the capacitor (100) has a capacitor length (21) in the longitudinal direction (132) between the first end (119) and the second end (121) and the ratio of the capacitor length (21) to the lower external terminal pitch is greater than about 4, and the lower external terminal pitch is less than about 250 µm; wherein the capacitor (100) has an insertion loss of -0.05 dB to -0.3 dB over a frequency range of 20 GHz to 40 GHz.