331results about "Structural fixed capacitor combinations" patented technology

To provide a laminated filter capable of improving performance.SOLUTION: A laminated filter 1 comprises a wall 13 which is disposed and grounded between a first inductor 11 and a second inductor 12. Therefore, electromagnetic coupling between the first inductor 11 and the second inductor 12 can be suppressed. A penetration part 30 penetrating in an opposing direction, in which the first inductor 11 and the second inductor 12 are opposed, is formed in the wall 13. In a lamination direction, a size of the penetration part 30 is larger than a size of one insulator layer 7. The wall 13 includes the large penetration part 30 to make a magnetic flux of the second inductor 12 which is a longitudinally wound inductor pass from the penetration part 30. Therefore, it is possible to suppress disturbance of the magnetic flux of the second inductor 12 to enhance a Q-value.SELECTED DRAWING: Figure 2

According to an embodiment, a biopotential measurement system includes an analog front-end and digital circuits. The analog front-end circuit includes a sensing electrode, a forward amplifier, and a feedback amplifier with an integration capacitor. A feature is the attenuation circuit between the forward and feedback amplifiers, which provides an attenuation factor determining the integration capacitor's value for achieving the desired high-pass corner frequency. With configurable attenuation factors, the system can process different biopotential signals. Multiple analog front-end circuits can be used to process different signals simultaneously. The digital circuit includes a processor for signal processing, dynamic adjustment of attenuation factors, and anomaly detection. Additional components like switched capacitors, pseudo-resistors, and multiplexers can enhance the system's functionality. The design allows flexible, multi-parameter physiological monitoring with adjustable frequency responses and gain settings.

Power converter (1) with: a switching circuit (20); a capacitor module (3) which is electrically connected to the switching circuit; an auxiliary capacitor module (5) connected in parallel to the capacitor module; and a device housing (12) which contains the switching circuit, the capacitor module and the auxiliary capacitor module, wherein The capacitor module includes: a capacitor element (31), a capacitor housing (32) that contains the capacitor element, an encapsulation resin (33) that encapsulates the capacitor element in the capacitor housing, and a capacitor busbar (4) which connects the capacitor element to a power terminal of the switching circuit, wherein the capacitor busbar includes: an element connection section (41) that is connected to the capacitor element within the encapsulation resin, a connecting section (42) which is connected to the power connection outside the encapsulation resin, and a power supply connection section (43) which is connected to a power supply wiring (54) outside the encapsulation resin, wherein the power supply wiring is electrically connected to a DC power supply, wherein the capacitor busbar includes a DC path (44) which represents a current path between the terminal connection section and the power supply connection section, and the DC path is exposed to the outside of the encapsulation resin, the auxiliary capacitor module is connected to the power supply connection section of the capacitor busbar, the auxiliary capacitor module is detachably attached to the power supply connection section by means of a fastening element (11), and a fastening direction of a fastening element (135) that secures the auxiliary capacitor module and a fastening direction of the fixing element are the same.

The reliability of an electronic device provided with a conductor pattern covered by a dielectric film is improved. An electronic device (100) is provided with: a substrate (110) including regions (111, 112); a resistance element (40) formed in the region (112); a dielectric film (21) covering the region (111) and the resistance element (40); a conductor pattern (31) formed in the region (111) via the dielectric film (21); an adhesion film (50) that does not cover the region (112) but covers the upper surface (31a) and the side surfaces (31b) of the conductor pattern (31); and a dielectric film (22) that covers the upper surface (31a) and the side surfaces (31b) of the conductor pattern (31) via an adhesion film (50).

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.

Provided is an electronic component that can suppress changes in characteristics even when stacking misalignment occurs. [Solution] The electronic component 1 comprises a base body 2, a capacitor conductor 32 having a main body portion 32A and a connection portion 32B electrically connecting the main body portion 32A to one terminal electrode, and a ground conductor 34 arranged within the base body 2 in a position opposite the capacitor conductor 32 in a second direction D2, wherein the ground conductor 34 has a first recess 34A when viewed from the second direction D2, and the connection portion 32B has a first portion 32Ba extending in the first direction D1 and having one end connected to the main body portion 32A, and a second portion 32Bb extending in a third direction D3 and having one end connected to the other end of the first portion 32Ba, wherein when viewed from the second direction D2, a part of the first portion 32Ba faces the ground conductor 34, and the second portion 32Bb is located in the first recess 34A.

Various aspects of the present disclosure generally relate to wireless communication, and to a pillar that includes one or more structures configured to define a capacitor. For example, a device (100) includes a die (102), a substrate (104), and a pillar (106) having an embedded capacitor. The pillar is electrically connected to one or more conductors of the die and to one or more conductors of the substrate. The pillar includes a first conductive structure (1102) and a second conductive structure (112). The pillar also includes a dielectric layer (114) disposed between the first conductive structure and the second conductive structure to define the embedded capacitor.

A filter device, method of manufacture and use thereof. The filter device comprises a foil-wound inductor formed by a first conductive foil strip having a first terminal and a second terminal, the first conductive foil strip wound around a core to form a plurality of winding layers such that the first terminal is proximate the core and the second terminal is located at an outermost winding layer, and a continuous dielectric insulating layer between the plurality of winding layers of the first conductive foil strip; and a tunable capacitor formed by a second conductive foil strip at least partially encircling the outermost winding layer of the foil-wound inductor and a dielectric insulating layer disposed therebetween, the second conductive foil strip having a portion that can be trimmed to alter a capacitance between the second conductive foil strip and the first or second terminal of the foil-wound inductor.

The invention aims to provide the capacitor which is convenient to combine, the circuit breaker is safe and reliable, and the capacitor can be quickly disassembled and assembled to realize quick reset. A PCBA terminal board is arranged on the lower shell, a circuit breaker is arranged above the PCBA terminal board, an upper shell is detachably installed on the upper portion of the lower shell, the circuit breaker is detachably installed on the inner wall of the upper shell, the circuit breaker can be taken out from the upper portion of the upper shell, a low-voltage capacitor unit is arranged on the lower portion of the lower shell and comprises a capacitor shell fixedly and detachably installed with the lower shell, and the capacitor shell is connected with the circuit breaker. The capacitor shell is provided with at least two capacitor modules, the capacitor modules are fixed on the drawer type slide rails, and the capacitor modules are provided with quick-plug conductive columns. Dual backup of mechanical bimetallic strip temperature protection and electronic protection is achieved, reliable action is achieved when the temperature reaches the preset temperature, response is rapid, and an overload, over-temperature and over-voltage comprehensive protection mechanism is achieved; rapid plugging and independent replacement of the capacitor module are realized, a drawer type slide rail structure is supported, and maintenance operation is facilitated.

A multi-layer device having a transparent or semi-transparent substrate; a solar cell layer coupled to the substrate; an energy storage layer coupled to the solar cell layer; and a converter layer coupled to the energy storage layer. The solar cell layer has a plurality of solar cells for receiving light through the substrate and converting energy of the received light into first electrical energy; the energy storage layer has one or more energy storage units for storing second electrical energy; and the converter layer has one or more power converters electrically connected to the solar cell layer and the energy storage layer for receiving the first electrical energy and the second electrical energy from the solar cell layer and the energy storage layer and outputting third electrical energy through an output thereof.

Provided is a stacked ceramic capacitor package, for an electronic device, preventing noise, vibration and cracks due to piezoelectric properties. The ceramic capacitor package for an electronic device comprises: stacked ceramic capacitors; a first terminal structure connected to a first side surface of the stacked ceramic capacitors; and a second terminal structure connected to a second side surface of the stacked ceramic capacitors and disposed so as to face the first terminal structure with the stacked ceramic capacitors therebetween. The first terminal structure has a first groove defined in an area coming into contact with the first side surface of the stacked ceramic capacitors. The horizontal length of the first groove is 30% to 50% of the horizontal length of the stacked ceramic capacitors.

The present invention improves the insertion loss of a resonant element. In the resonant element (10), a first via electrode (111) and a second via electrode (112) connect a first planar electrode (101) and a third planar electrode (103). A third via electrode (113) and a fourth via electrode (114) connect the first planar electrode (101) and a second planar electrode (102). When the first planar electrode (101) is viewed from the normal direction (Z) of the first planar electrode (101), a first imaginary line (VL11) connecting the first via electrode (111) and the second via electrode (112) and a second imaginary line (VL12) connecting the third via electrode (113) and the fourth via electrode (114) cross.

A capacitor includes a case that houses a capacitor element, a filling resin filled in the case, and a bus bar. The filling resin includes an exposed surface exposed to the outside. The bus bar includes a protruding part protruding from the inside of the filling resin to the outside, a flat surface part, and a first external connection terminal part. The flat surface part includes a first end and a second end that is connected to the protruding part and the first external connection terminal part. The protruding part is bent at the second end around a first axis to extend in a first direction, and the first external connection terminal part is bent at the second end around a second axis to extend in a second direction opposite to the first direction. Each of the first axis and the second axis is disposed in a plane facing the exposed surface.

A power conversion device according to the present disclosure includes a capacitor, a power module configured to convert a voltage from the capacitor and output the converted voltage, and a connection conductor including a positive electrode-side busbar configured to connect the capacitor and a P-type terminal of the power module, and a negative electrode-side busbar symmetrically arranged side by side with the positive electrode-side busbar with a gap therebetween and configured to connect the capacitor and an N-type terminal of the power module. The positive electrode-side busbar includes a first main body portion including a first bottom surface abutting on the P-type terminal and a first opposing surface rising from the first bottom surface and a first cutout portion formed in at least part of the first main body portion on a side opposite to the first bottom surface and the first opposing surface. The negative electrode-side busbar includes a second main body portion including a second bottom surface abutting on the N-type terminal and a second opposing surface rising from the second bottom surface and disposed opposed to the first opposing surface with a gap therebetween and a second cutout portion formed in at least part of the second main body portion on a side opposite to the second bottom surface and the second opposing surface.

An integrated structure comprising: a substrate (100, 101), a conductive layer, the conductive layer having a first cavity, the first cavity (102C) being filled with a first insulating region (103F), the first insulating region having a top surface flush with a top surface of the conductive layer to form a first planar surface (F1), a protective liner (104) on the top surface of the conductive layer and the top surface of the first insulating region, an anodization barrier layer (105) on the protective liner, the protective liner and the anodization barrier layer having a second cavity (105_104C) passing through the protective liner and the anodization barrier layer and opening onto the first insulating region, the second cavity being filled with a second insulating region (106F), the second insulating region having a top surface flush with a top surface of the anodization barrier layer to form a second planar surface (F2).

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

Electronic component, which includes: a layered busbar structure (212) comprising at least two busbar layers (212A-C) separated by an insulating layer; a transistor (214) connected to the layered busbar structure (212) on a first side thereof; and a capacitor (100) which is mounted on the first side of the layered busbar structure (212) and is positioned further away from the layered busbar structure (212) than the transistor (214), wherein the capacitor (100) has respective planar terminals (102, 104) which are parallel to each other and perpendicular to the layered busbar structure (212), wherein each of the planar terminals (102, 104) comprises a rectangular element, one side of which is connected to the capacitor (100) and the opposite end is connected to a corresponding busbar layer (212A-C), wherein each of the planar terminals (102, 104) has several feeder lines (108, 110) at the opposite end of the rectangular element, the feeder lines (108, 110) connecting the respective planar terminal (102, 104) to the corresponding busbar layer.

A capacitor assembly is presented comprising a first to fourth individual capacitor, each with a first cover surface defining a respective normal direction of the individual capacitor, and a second cover surface on the opposite side, wherein the first cover surface of the first individual capacitor defines a main direction, with first connection elements arranged on the first cover surface and second connection elements arranged on the second cover surface, wherein the individual capacitors are arranged side by side in a 1x4 matrix, wherein the normals of the first and third individual capacitors point in the main direction and wherein the normals of the second and fourthsingle capacitors pointing in the opposite direction to the main direction, wherein all first connection elements are connected to each other by means of a first busbar, and wherein all second connection elements are connected to each other by means of a second busbar, and wherein a first intermediate section of the first busbar and a first intermediate section of the second busbar between the first and second single capacitors, and a second intermediate section of the first busbar and a second intermediate section of the second busbar between the third and fourth single capacitors are arranged one above the other and each separated by a second insulating device.

To equalize apportionment of a current at switching time among semiconductor modules connected in parallel to one another.SOLUTION: A laminated wiring 13 includes: a first conductor 13a which connects terminals 11a1-11d1 of capacitors 11a to 11d and each positive terminal 12a1-12f1 of a plurality of semiconductor modules 12a-12f; a second conductor 13b which connects terminals 11a2-11d2 of the capacitors 11a-11d and each negative terminal 12a2-12f2; and an insulator 13c. Slits 13a1-13a5, 13b1-13b5 are formed at least one of the first conductor 13a and the second conductor 13b (in both of them in the example of FIG. 1), and thereby among the semiconductor modules 12a-12f, a variation in a total of respective inductance values between the respective terminals 11a1-11d1 and one positive terminal 12a1-12f1 closest to the respective terminals and respective inductance values between the respective negative terminals 12a2-12f2 and one terminal 11a2-11d2 closest to the respective negative terminals is smaller than or equal to 10 nH.SELECTED DRAWING: Figure 1

A semiconductor device includes a substrate (100); a first terminal (A) and a second terminal (B); and a conductor (210) arranged on the substrate (100) between the first terminal (A) and the second terminal (B) to constitute an inductor (IN) shaped for forming a first loop (LI) and a second loop (L2). A first crossing (C) of the conductor (210) with itself is present between the first loop (LI) and the second loop (L2). The first loop (LI) and the second loop (L2) define a first enclosed area and a second enclosed area, respectively. The first enclosed area is smaller than the second enclosed area.

To reduce the chip size of a chip-type electronic component including a capacitor and an inductor. A chip-type electronic component includes a capacitor constituted by a lower electrode pattern, an upper electrode pattern, and an insulating layer, an insulating layer covering the capacitor, and an inductor pattern disposed on the insulating layer. The inductor pattern has a section overlapping the capacitor, whereby an auxiliary capacitor is added. The inductor pattern is thus made to partly overlap the capacitor, so that a larger inductance can be obtained with a small chip size. In addition, characteristics can also be improved by auxiliary capacitance.

Provided is a switching power source device (80) equipped with a composite power inductor (10), the switching power source device comprising: a linear inductor conductor (31); a linear inductor conductor (32); an inductor conductor (33); and one magnetic body (20) that forms a magnetic path of a magnetic flux generated by a current flowing to the inductor conductor (31), the inductor conductor (32), and the inductor conductor (33). One end of the inductor conductor (31) is connected to a first input terminal, and the other end is connected to one end of the inductor conductor (33). One end of the inductor conductor (32) is connected to a second input terminal, and the other end is connected to one end of the inductor conductor (33). The inductor conductor (31), the inductor conductor (32), and the inductor conductor (33) are sandwiched by or contained in the magnetic body (20). The inductor conductor (31) and the inductor conductor (32) are arranged in parallel so that the magnetic fluxes generated by the current flowing to each conductor are cancelled out at an inner leg section (10ZI) of the magnetic body (20) between the inductor conductor (31) and the inductor conductor (32), and the magnetic fluxes generated by the current flowing to each conductor are intensified at outer leg sections (10ZO1, 10ZO2) of the magnetic body (20) on the outside of the inductor conductor (31) and the inductor conductor (32). The inductor conductor (33) is arranged so that a plane created by the magnetic flux generated by the current flowing to the inductor conductor (33) is orthogonal to the planes created by the magnetic fluxes generated by the current flowing to the inductor conductor (31) and the inductor conductor (32). The inductor conductor (31) and the inductor conductor (32) are inductors that constitute a power conversion circuit, and the inductor conductor (33) is an inductor that constitutes a low-pass filter with respect to an output current of the power conversion circuit.

This electronic component has a first external electrode, a base body part, and a second external electrode that are disposed in order in a first direction. A direction opposite to the first direction is defined as a second direction. A direction orthogonal to the first direction is defined as an orthogonal direction. The first external electrode includes: a first external electrode body which is spaced apart from the base body part and disposed in a second direction relative to the second external electrode; and a first external electrode extension part extending in the first direction from an edge section of the first external electrode body. The second external electrode includes: a second external electrode body which is spaced apart from the base body part and disposed in the first direction relative to the first external electrode; and a second external electrode extension part extending in the second direction from an edge section of the second external electrode body. A portion of the first external electrode extension part and a portion of the second external electrode extension part constitute a pair of facing parts facing each other in the orthogonal direction. An insulating layer is provided between the pair of facing parts.

A DC block structure includes a dielectric (1), transmission lines (2a, 2b) having characteristic impedance of 50 Ω and formed on a surface of the dielectric (1), transmission lines (3a, 3b) formed on the surface of the dielectric (1) so as to be connected with the transmission lines (2a, 2b) and designed so that characteristic impedance is higher than the characteristic impedance of the transmission lines (2a, 2b), and a capacitor (4) mounted on the transmission lines (3a, 3b) so as to connect the transmission line (3a) and the transmission line (3b) in series.

Fixed capacitor (10) for an electronic device of a motor vehicle, in particular a power converter (12) for the electric drive of the motor vehicle, with a case (24), a first electrode (16) provided inside the housing (24), a second electrode (18) separated from the first electrode (16) by an intermediate space (20) and cooperating with the first electrode (16) to generate an electric field inside the housing (24) and a dielectric provided in the space (20), the housing (24) has an inlet (32) communicating with the space (20) and an outlet (34) communicating with the space (20), and the dielectric is a coolant (28) of the motor vehicle, wherein at least one electrically non-conductive spacer is arranged in the space (20) to define a distance between the first electrode (16) and the second electrode (18), wherein within the space (20) a flow path for the coolant (28) leading from the inlet (32) to the outlet (34) is kept clear and in the space (20) an electrically non-conductive porous body (22) is provided to form the spacer, wherein the porous body (22) has a sponge-like structure.

A method of determining a lifetime parameter of a capacitor in a failsafe device includes measuring an amount of energy required to return the failsafe device to a failsafe position, measuring an effective capacitance of the capacitor, and comparing the amount of energy to the effective capacitance to determine the lifetime parameter of the capacitor.

The invention relates to a mounting structure (3) for a capacitor (4) in a housing part (9). The housing part (9) comprises a bottom (5) and a cover (9C) part. The mounting structure (3) is an integral part of the bottom (5) of the housing part (9): The mounting structure (3) is at least defined by a first pair (11) and a second pair (12) of two opposing holding elements (13). The housing (2) comprises at least one pair of locking features (42) that interact with the at least one pair of extensions (40). The pair of extensions (40) limit a radial defection (DR) of the opposing holding elements (13) and thereby secure the capacitor (4) in the mounting structure (3).

A multilayer bandpass filter includes an LC resonator inside a multilayer body of stacked dielectric layers. The LC resonator has a loop shape arranged such that a winding axis is perpendicular to a stacking direction of the multilayer body. The LC resonator includes a capacitor conductor pattern, a line conductor pattern and a GND conductor pattern connected by first and second interlayer connecting conductors extending in the stacking direction. A capacitance portion is formed where at least a part of the capacitor conductor pattern and at least a part of the GND conductor pattern face each other on different layers. A length of the first interlayer connecting conductor in the stacking direction defines a “via length” and a gap between the first and second interlayer connecting conductors defines a “line length.” The via length is longer than the line length.