50results about How to "Improve RF characteristics" patented technology

In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

The invention discloses a low-temperature sintering ceramic dielectric material comprising the following components by weight percent: 50-70wt% of main crystal phase, 0-13.4wt% of modified additive and 16.6-40.5wt% of glass fusion aid. The main crystal phase is alumina Al2O3. The modified additive is one or several of BaO, TiO2, MgO and CaO. The glass fusion aid is one or several of SiO2, ZnO, B2O3 and BiO. The method for preparing a ceramic capacitor by the ceramic dielectric material comprises the processes of pulping, flow casting, silk screen printing, laminating, cutting, sintering and end capping, and the sintering temperature is 800-1000 DEG C. The dielectric material conforms to the NPO ceramic dielectric property and has good environmental-protection property, high material dispersivity, good formation process and no cracking when being sintered.

In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT.

The invention discloses a GaN (Gallium Nitride) HEMT (High Electron Mobility Transistor) device and a preparation method thereof. The GaN HEMT device comprises an N-type cap layer, a first passivationlayer and a first dielectric layer, wherein a gate metal region is penetrated in the middle parts of the N-type cap layer, the first passivation layer and the first dielectric layer; a second passivation layer is formed in the gate metal region and covers the lateral surfaces of the N-type cap layer, the first passivation layer and the first dielectric layer exposed in the gate metal region and apart of the upper surface of a barrier layer; a second dielectric layer is formed in the gate metal region and is superposed on the second passivation layer; a gate metal layer covers the residual upper surface of the barrier layer exposed in the gate metal region, the second passivation layer and the second dielectric layer; and the second passivation layer and the second dielectric layer are superposed at two sides of the gate metal layer. The N-type cap layer is adopted to reduce the parasitic resistance of a source and a drain, and a lateral wall process is adopted to manufacture the second passivation layer and the second dielectric layer which are superposed at two sides of the gate metal layer to reduce the gate length size and reduce the parasitic capacitance, thereby obtaining the GaN HEMT device with excellent radio frequency characteristics.

The invention relates to an electrothermal-driven in-plane bistable radio frequency microswitch belonging to the technical field of micro electromechanics. The electrothermal-driven in-plane bistable radio frequency microswitch comprises an electrothermal-driven mechanism, a mechanical locking mechanism and a signal conversion mechanism, wherein the electrothermal-driven mechanism is positioned under the mechanical locking mechanism; and the mechanical locking mechanism is connected with the signal conversion mechanism. The invention can realize the mechanical locking by using a pair of locking contacts, does not require continuous power consumption when keeping in a stable state, also fully develops the advantages of large driving force, high displacement power density and convenient integrated manufacture of an electrothermal driver and can be used as the actuation form of the mechanical locking structure of the switch. The switch has simple structure, foreseeable radio frequency (RF) characteristic, possibility of batch manufacture and practical application and suitability for integral manufacture.

An antenna module (1) according to the present disclosure has a dielectric substrate (20), an array antenna (10) including a plurality of patch antennas (111), an RFIC (40) electrically connected to the plurality of patch antennas (111), a signal conductor post (131) electrically connected to the RFIC (40), and a ground conductor post (132) set at a ground potential. The ground conductor post (132) is arranged, when viewed from a direction perpendicular to a first main surface of the dielectric substrate (20), between the signal conductor post (131) and a first side surface closest to the signal conductor post (131) of the dielectric substrate (20) in a polarizing direction of radio frequency signals to be emitted or received by the plurality of patch antennas (111).

A coaxial cable (60) is used for transmitting a low frequency signal and an RF signal to a receiver main body (120). At the time of using an earphone antenna connecting device by soldering it to pins of a pin plug connector (110) used for connecting with the coaxial cable, a conversion board is provided for pins (11~ 20) of a 10 pin plug connector (115), and a rear plane of a pattern of the conversion board is used for grounding, except a pin inserting slot (100) of the pin (20) connected with an antenna signal line (9). Pin inserting slots (134A, 135A, 132A) into which audio signal pins (14, 15) and a microphone pin (12) for transmitting low frequency waves such as voice are surrounded from at least three sides. Thus, noise in devices from a voice signal and a microphone signal is reduced, high frequency signal transmission characteristics are improved by the connector, and the degree of freedom in board layout is improved.

An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.

A multilayer coil component includes a multilayer body formed by stacking a plurality of insulating layers and including a coil built therein, and first and second outer electrodes electrically connected to the coil. The coil is formed by electrically connecting a plurality of coil conductors stacked together with the insulating layers. The multilayer coil component further includes, inside the multilayer body, first and second connecting conductors. The first connecting conductor connects between a portion of the first outer electrode covering the first end face, and a coil conductor facing the portion. The second connecting conductor connects between a portion of the second outer electrode covering the second end face, and a coil conductor facing the portion. Concerning the length direction, the first and second connecting conductors each have a length from about 2.5% to about 7.5% of the length of the multilayer body.

The invention discloses a radio frequency switch circuit. The radio frequency switch circuit comprises a grid voltage control module for establishing the grid control voltage (VCG) for controlling on-off of a switch module, a body voltage control module for establishing the body control voltage (VCB) for controlling on-off the switch module and the switch module controlled by the grid control voltage (VCG) and the body control voltage (VCB) to connect or not connect a radio frequency input signal (RFin) to a radio frequency output end (RFout). The radio frequency switch circuit can optimize and reduce the on resistance (Ron) at a circuit layer and optimize the on-off time.

The invention discloses a vertically-integrated double-gate MOSFET structure and a preparation method therefor. Compared with a conventional planar MOSFET structure, the vertically-integrated double-gate MOSFET structure adopts an III-V group semiconductor material with high electron mobility / hole mobility as a channel material; due to the adopted double-gate structure, the gate control capability of an MOSFET device is effectively improved, and influence from a short channel effect and the like is reduced; an NMOS and a PMOS are integrated in a vertical direction, so that the integration degree of devices on a unit wafer area is improved; and vertical through holes are adopted to realize interconnection of the devices in the vertical direction, so that the length of an interconnecting lead is effectively shortened while the operation speed of the devices is improved. The vertically-integrated double-gate MOSFET structure provided by the invention has an important application value in a post-Moore era CMOS integration technology and a high-performance III-V group semiconductor device.

The invention discloses a detuning magnetic resonance radio frequency coil without an external direct current circuit. The detuning magnetic resonance radio frequency coil comprises a driving detuning circuit and a resonance capacitor, wherein the driving detuning circuit and the resonance capacitor are in serial connection, two parallel resonance inductors formed by coated copper of a printed circuit board are arranged between the driving detuning circuit and the resonance capacitor, and the two parallel resonance inductor form a loop and are connected with a direct-current power supply used for driving the driving detuning circuit. The detuning magnetic resonance radio frequency coil has the advantages of mutually offsetting magnetic fields generated by direct current to the maximum degree and being small in effect on evenness of a main field, small in cross interference, good in radio frequency characteristic, small in occupancy and simple in circuit structure.

The invention relates to a flexible thin film radio frequency switch which comprises a substrate. The substrate is a flexible substrate, a SU8 adhesive layer is arranged on the substrate, and a first PIN diode, a second PIN diode, an input end, an output end and a ground terminal are respectively arranged on the upper surface of the SU8 adhesive layer, wherein one end of the first PIN diode is connected with the input end by a metal interconnection line; the other end of the first PIN diode is respectively connected with the output end and one end of the second PIN diode by metal interconnection lines; and the other end of the second PIN diode is connected with the ground terminal by a metal interconnection line. The invention provides the switch which is developed by combining a thin film transfer process and utilizing the flexible PIN diodes and can be applied to the field of flexible radio frequency. A production process of the flexible thin film radio frequency switch disclosed by the invention is completely compatible to a flexible thin film diode, the PIN diodes and the like. The flexible thin film radio frequency can be applied to numerous wireless portable devices, such as a mobile phone and a radar system. By combined use of the monocrystal silicon thin film transfer process, the switch with a low parasitic resistance and a high radio frequency characteristic is implemented.

A radio frequency signal RF is input to a base of each of transistors TR1 through TRn via a corresponding capacitor among capacitors C1 through Cn, is amplified, and is output from a collector of each of the transistors TR1 through TRn. An emitter of each of the transistors TR1 through TRn is grounded. A bias voltage DC given from a bias circuit Bias is supplied to the base of each of the transistors TR1 through TRn via a corresponding resistor among resistors Ra1 through Ran. A signal line for the bias voltage DC is connected to an input line for the radio frequency signal RF via the bridge resistor R in a direct current manner.

A transistor integrated circuit apparatus generating less noise, having superb RF characteristics, and preventing thermal runaway of transistors is provided. Owing to capacitors C11 through C1n having one end commonly connected to an RF signal input terminal RFin and the other end connected to a base electrode of a corresponding transistor, and inductors L11 through L1n having one end commonly connected to a DC power supply input terminal DCin and the other end connected to a base electrode of a corresponding transistor, RF noise generated in a DC power supply circuit is reduced. This can reduce the RF noise output from the transistors Tr11 through Tr1n. The inductors L11 through L1n prevent an RF signal input from the RF input terminal RFin from flowing toward the DC power supply circuit. This can prevent the RF signal from being lost by the flow thereof toward the DC power supply circuit.

The invention discloses a double-gate MOSFET structure and a preparation method thereof, and belongs to the technical field of semiconductor integration. The double-gate MOSFET structure sequentially comprises a first gate metal layer, an III-V group semiconductor channel layer, an III-V group semiconductor source drain layer and a second gate metal layer from bottom to top, wherein the first gate metal layer and the second gate metal layer form the double-gate structure; the III-V group semiconductor channel layer and the III-V group semiconductor source drain layer are made of an III-V group semiconductor material. Due to adoption of the double-gate structure, the gate control property of an MOSFET device can be effectively improved, and influence caused by short channel effects and the like can be reduced. As a back gate structure is achieved by using a through hole technique, parasitic capacitance can be effectively reduced, and the radio properties of a device are improved. The double-gate MOSFET structure disclosed by the invention is integrated on a silicon substrate, and single chip integration with other silicon-based CMOS integrated device can be achieved.

The invention discloses an III-V MOS device and a production method. The production method comprises the following sequential steps: forming a channel layer on a semiconductor layer on a substrate; forming an ohmic contact layer on the semiconductor channel layer; making silicon dioxide medium pores in the ohmic contact layer; etching the ohmic contact layer by an etching method; making a SiO2 side wall; depositing a high-k medium in the channel by an atom layer depositing method; making a gate metal; etching the high-k medium and silicon dioxide except the gate metal by taking the gate metal as a mask to expose the ohmic contact layer; and depositing source-drain metals in an active area by an evaporation technology to finish the production of the MOSFET device. The production method of the device can be used for producing a digital integrated circuit; and after the production of gate and source and gate-source gap, the radio-frequency characteristic is improved, and the method also can be applied to a radio-frequency integrated circuit.

The invention discloses a radiofrequency LDMOS (laterally diffused metal oxide semiconductor) device. Drift regions are uneven doping structures; a first drift region, a third drift region and a second drift region are sequentially arranged between a channel and a drain region; the doping concentration of the first drift region is minimum, the strength of an electric field nearby a channel region and a hot carrier effect can be reduced, and the reliability of the device is improved; the doping concentration of the second drift region is high, and the switch-on resistance of the device can be reduced; and by a contra-doping covering layer formed on the surface of the second drift region, the drift regions can run out effectively, the outputting capacitance of the device is reduced, influences of charge and an interface state of shielding dielectric layer without a Faraday shield layer can be avoided, and the characteristics of the device are stable. The second drift region is a transition region, and the driving current of the device can be increased further and the switch-on resistance of the device can be reduced under the condition that the reliability and the outputting capacitance of the device are not affected. The invention also discloses a manufacturing method of the radiofrequency LDMOS device.

A signal detection contactor has a contactor main body and a plurality of coaxial bodies. Each coaxial body includes a core wire. The core wire is used for coming into contact with a probe of a prober and for receiving a signal transmitted from a tester, in order to calibrate a phase difference among signals transmitted through a plurality of probes.

The invention relates to a method of manufacturing a structure suitable as an internal antenna in small radio devices, and an antenna element to which the method is applied. The antenna element comprises a radiating plane and additionally e.g. supportive elements, a feed conductor and short-circuit conductor as well as extensions to increase capacitance. The antenna element is fabricated by first extruding from a billet an antenna billet, and working the latter as required. The antenna billet may be symmetrical so that two antenna elements will be produced when it is cut in half. Advantageously the antenna element is fabricated so as to conform with the covering of the device in which it is placed. It may also be part of a covering of a device. The manufacturing costs of the antenna element are relatively low and the radio characteristics of the element are good. An antenna structure employing the element has got few separate parts and is mechanically firm and space-conserving. <IMAGE> <IMAGE>

The invention provides a semiconductor device and a forming method thereof. The forming method of the semiconductor device includes: providing first and second wafers; forming a plurality of trenches; forming a first oxide layer on the second wafer; The circle is bonded to the first wafer, the first wafer is used as the substrate of the semiconductor device, the first oxide layer is used as the buried oxide layer, and the second wafer is used as the top silicon for forming the device. The semiconductor device includes: a substrate; a second oxide layer located on the surface of the substrate; a first oxide layer; the first and second oxide layers together form a buried oxide layer; a first side of the substrate opposite to the buried oxide layer There are a plurality of trenches; the semiconductor device also includes a top layer of silicon formed on the buried oxide layer. The beneficial effect of the present invention is that the carriers accumulated on the surface of the substrate close to the buried oxide layer will be blocked by the trench, reducing the impact of the carriers on the capacitance, thereby reducing the variable capacitance of the interface under the buried oxide layer. With the amount of change, the radio frequency characteristics of the semiconductor device are improved.

A dielectric ceramic composition suitable for radio frequency applications, comprising a crystalline main component having a perovskite crystal structure, and an auxiliary component. The crystalline main component is represented by the following chemical formula: (1-x)MeTiaO1+2a-xLn(Ma1 / 2Mb1 / 2)bO(3+3b) / 2 wherein Me is at least one of Ca and Sr; Ln is a rare earth element; Ma is at least one of Mg and Zn; Mb is at least one of Sn and Zr; x represents the mole fraction of Ln(Ma1 / 2Mb1 / 2)bO(3+3b) / 2 ; and a and b represent the molar ratio, where 0.95≤a≤1.05, 0.9≤b≤1.05 and 0.3≤x≤0.5. The auxiliary components contain B and Si. The composition can be sintered at a temperature of 1,000°C or lower. An electronic component includes a ceramic component of a dielectric ceramic composition, and a conductor placed inside the ceramic component.

An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.

The present invention discloses to an SMA connector, a preferable embodiment of which comprises a body acting as ground, a central conductor existing in the inner part of the ground, an insulator with a predetermined dielectric constant existing between the body and the central conductor, a first step transition part formed in the body, a taper formed in the central conductor in order to improve RF characteristics and to fix the central conductor and the insulator, and a second step transition part formed in the central conductor corresponding to the first step transition part to improve RF characteristics.

The invention discloses a flowing terminal radio frequency testing switch, including a first terminal (500), a second terminal (600), a casing (700) which is used for containing the first terminal (500) and the second terminal (600) and an outer casing (800) around the casing (700). The flowing terminal radio frequency testing switch is characterized in that the first terminal (500) includes a first vertical slab (510), an elastic backing block (520) which is inflected at the lower half part of the first vertical slab (510), a connecting port joining component (530) which is formed by inflecting the elastic backing block (520) upwardly to be zigzag, a first joining block (540) which is formed by extending forward from the connecting port joining component (530) and a first support plate (550) which is inflected backward at the end of the lower part of the first vertical slab (510); the second terminal (600) includes a second vertical slab (610), a second support plate (650) which is extended laterally from the second vertical slab (610), and a second joining block (640) which is extended upwardly from the end of the upper part of the second vertical slab (610); the thickness of the first terminal (500) is 0.1mm to 0.12mm; the width of the elastic backing block (520) is 0.5mm to 0.6mm; the total height after the combination of the first terminal (500), the second terminal (600), the casing (700) and the outer casing (800) is 2.45mm to 2.5mm; one edge of the end of the upper part of the second joining block (640) of the second terminal (600) is a chamfered edge; the width of the second joining block (640) is 0.4mm to 0.5mm; the surface of the outer casing (800) is formed by firstly coating a nickel coating (910) which is made from sulfamic acid and 1micron to 2 microns thick and a gold coating (920) which is 0.08 micron to 0.2 micron thick in turn and then being pressed.

A signal detection contactor has a contactor main body and a plurality of coaxial bodies. Each coaxial body includes a core wire. The core wire is used for coming into contact with a probe of a prober and for receiving a signal transmitted from a tester, in order to calibrate a phase difference among signals transmitted through a plurality of probes.

The invention discloses a germanium-based silicon germanium reduced-field layer LDMOS device structure which comprises a P-type germanium channel layer, an N-type doped germanium drift layer, a heavy N-doped germanium ohmic contact layer, a growth layer with separation of silicon germanium and germanium as a drift layer, a P type doped silicon germanium drift reduced field layer, a gate slot structure with a depth reaching the P-type germanium channel layer, an oxide dielectric layer formed in a gate slot, a gate metal layer formed in the gate slot, and source and drain metal electrodes formed at source and drain areas in order.

A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.