Double-gate MOSFET structure and preparation method thereof

Abstract

The invention discloses a double-gate MOSFET structure and a preparation method thereof, and belongs to the technical field of semiconductor integration. The double-gate MOSFET structure sequentially comprises a first gate metal layer, an III-V group semiconductor channel layer, an III-V group semiconductor source drain layer and a second gate metal layer from bottom to top, wherein the first gate metal layer and the second gate metal layer form the double-gate structure; the III-V group semiconductor channel layer and the III-V group semiconductor source drain layer are made of an III-V group semiconductor material. Due to adoption of the double-gate structure, the gate control property of an MOSFET device can be effectively improved, and influence caused by short channel effects and the like can be reduced. As a back gate structure is achieved by using a through hole technique, parasitic capacitance can be effectively reduced, and the radio properties of a device are improved. The double-gate MOSFET structure disclosed by the invention is integrated on a silicon substrate, and single chip integration with other silicon-based CMOS integrated device can be achieved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integration, in particular to a double-gate MOSFET structure and a preparation method thereof. Background technique [0002] As the core and foundation of the information industry, semiconductor technology is regarded as an important symbol to measure a country's scientific and technological progress and comprehensive national strength. In the past 40 years, the integrated circuit technology based on silicon CMOS technology has followed Moore's law to increase the working speed of the chip, increase the integration level and reduce the cost by reducing the feature size of the device. The feature size of the integrated circuit is reduced from the micron scale. to the nanoscale. However, when the gate length of MOS devices is reduced to the 90nm technology node, traditional silicon-based CMOS devices are facing more and more problems. The introduction of new structures and new materials has b...

AI Technical Summary

Problems solved by technology

However, due to the relatively large contact area between the back gate and the channel and the source and drain of the traditional double-gate structure MOSFET, the parasitic capacitance is relatively large, which limits the radio frequency performance of the double-gate device. Reduced contact area between source and drain

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