140 results about "Equivalent series inductance" patented technology

A capacitor element includes a positive electrode body made of valve metal, a dielectric oxide layer on the positive electrode body, a solid electrolytic layer made of conductive polymer on the dielectric oxide layer, and a negative electrode layer on the solid electrolytic layer. A solid electrolytic capacitor includes the capacitor element, a package made of insulating resin covering the capacitor element, a base electrode provided at an edge surface of the package and made of non-valve metal coupled with the positive electrode body, a diffusion layer for connecting the positive electrode body to the base electrode, an external electrode on the base electrode, and an external electrode connected to the negative electrode layer. The solid electrolytic capacitor reduces the number of components and processes to reduce its cost and to have a small size, and has a small equivalent series resistance and a small equivalent series inductance.

The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Internal dielectric layers isolated between them by a ceramic layer are arranged in a dielectric body, other internal conductor layers also isolated between them by a ceramic layer are arranged in the dielectric body by being isolated from the above internal conductor layers. Each of the all internal conductor layers is formed with a cut part, and a channel part is formed around the cut part, and the channel parts are arranged so that currents flow in mutually reverse directions between channel parts of internal conductor layers adjoining across a ceramic layer. Consequently, the equivalent serial inductance of the multilayer capacitor is largely reduced and fluctuations of a power source voltage of a CPU is made small.

Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.

Disclosed are apparatus and methodology for providing land grid feedthrough capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Low equivalent series inductance (ESL) is provided by current cancellation techniques involving opposite current flow in power or signal and ground current paths through the device.

A single element of an ultrasonic transducer includes at least one combination of an equivalent series capacitor C1, an equivalent series inductor L1, and an equivalent series resistance R1. The ultrasonic transducer further includes an equivalent parallel capacitor C0. An inductor L2 is connected in series between the ultrasonic transducer and the drive circuit. A first resonance frequency of the equivalent series capacitor C1 and the equivalent series inductor L1 is F0. A second resonance frequency determined by at least the equivalent parallel capacitor C0 and the inductor L2 is Fp. A drive circuit drives the ultrasonic transducer while switching the driving frequency of the ultrasonic transducer to one of the resonance frequency F0 and the resonance frequency Fp.

The invention relates to a high-density capacitor and an electrode leading-out method thereof, wherein the capacitor comprises a substrate, on which a plurality of local electrode layers grow, the local electrode layers include even local electrode layers and odd local electrode layers matched with the even local electrode layers, and high dielectric constant dielectric layers are arranged between the odd local electrode layers and the even local electrode layers, interconnection electrode layers comprising even interconnection electrodes and odd interconnection electrodes are arranged above the substrate, and the odd interconnection electrodes are isolated from the even interconnection electrodes in an insulating manner. The capacitor provided by the invention has the advantages of high electric capacity, small equivalent series inductance and adjustable equivalent series inductance; and the equivalent series inductance can be regulated according to the demands of the circuit so as to reach the best matching. With the advantages of high precision, high reliability, small volume, long service life and environmental protection, the product is widely used for decoupling a high frequency circuit and removing noise; and the product can be used in a common tank circuit. The capacitor can be integrated in an IC (integrated circuit) chip or packaged in a same package together with the IC easily.

Provided is an aluminum electrolytic capacitor with reduced ESR (equivalent series resistance) and ESL (equivalent series inductance). In an aluminum electrolytic capacitor including a capacitor element 1 having an anode side lead terminal 3 for anode lead-out and a cathode side lead terminal 5 for cathode lead-out, a bottomed exterior case 9 in which the capacitor element 1 is stored, and a seal rubber 8 sealing the opening part of the bottomed exterior case 9, there is a terminal structure having the selected number of the anode side and cathode side lead terminals 3 and 5 from the range within 2 to 4, respectively. By this plural terminal structure, there is a circuit in which ESR and ESL are equivalently arranged in parallel. Thereby, the resistance of the lead terminal that is the ESR component and the connection resistance between foil and the lead terminal are eliminated, so the ESR can be reduced. Moreover, the influence of inductance of the lead terminal can be removed, so the ESL can be reduced.

The invention discloses a liquid crystal electrical control zero-crossing scanning leaky wave antenna based on comb-line waveguide, which belongs to the technical field of microwave antenna construction. The problems that a conventional electrical control scanning leaky wave antenna based on a varactor and other traditional electric tuning elements difficultly works in a microwave high frequency band and the existing liquid crystal electrical control fixed-frequency scanning leaky wave antenna is difficult to realize zero-crossing scanning and requires a bias circuit which is specially designed are solved. The antenna provided by the invention comprises a top dielectric plate layer, a metal layer, a liquid crystal layer and a bottom waveguide groove. The metal layer is arranged between the top dielectric plate layer and the bottom waveguide groove. A longitudinal groove structure is arranged on the upper surface of a rectangular plate to form the bottom waveguide groove. The metal layer is in a comb-line structure. N periodic slit units are arranged between two columns of comb teeth on the comb-line structure. N periodic slit units comprise two groups of vertical slit columns and a group of transverse slit column. Through periodic transverse slits, the equivalent series inductance of electromagnetic waves spreading between the bottom waveguide groove and the metal layer is increased. Through periodic vertical slits, the equivalent parallel capacitance is increased.

The invention discloses a method for reducing power-supply ripples of an active matrix light-emitting display, comprising the following steps of: a) obtaining equivalent series inductance ESL, equivalent series resistance ESR and capacitance c of a panel parasitic capacitor of the active matrix light-emitting display varying with frequency, and obtaining a conversion factor a from a gray-scale level to a load level of a display panel; b) taking frame or line as unit to count the gray-scale level N to be displayed of each frame or each line, and estimating the load level; c) calculating a load equivalent voltage drop Vdroop according to the estimated load level; d) generating an offset voltage Voffset by serially connected L, R and C, wherein the Voffset is almost equal to the load equivalent voltage drop Vdroop; and e) outputting the offset voltage by a power supply module, and displaying the current frame or line. In the method for reducing the power-supply ripples of the active matrix light-emitting display, the load equivalent voltage drop is estimated and compensated, so that negative effect caused by the power-supply ripples is reduced, and image quality is improved.

A multi-terminal monolithic ceramic capacitor arranged to reduce an equivalent series inductance and having an array structure is provided. A first same-polarity-connection conductor and a second same-polarity-connection conductor are provided inside a capacitor body so as to extend over at least two capacitors. The first same-polarity-connection conductor is electrically connected to a plurality of first external terminal electrodes, and the second same-polarity-connection conductor is connected to a plurality of second external terminal electrodes. In the monolithic ceramic capacitor which is mounted on a wiring substrate, the overall capacitance can be maintained even if an accident, such as cracking of a solder joint, occurs in one of the external terminal electrodes.

An improved electrical terminal attachment process for a wound polymer film/foil or metallized film capacitor is described that minimizes thermal damage to the capacitor structure and improves the current carrying capability of the capacitor. The process employs an electrically conductive adhesive that can be cured at low temperatures. The disclosed process improves the reliability of the capacitor when used at high RMS or pulsed currents. It also enables capacitor application structures with reduced equivalent series inductance that would be otherwise difficult or impossible to fabricate.

The present invention discloses an interleaving LCLC resonant converter with a wide load and a wide gain. The interleaving LCLC resonant converter comprises an input direct current source, two primaryinversion networks, two first resonance inductors, two first resonance capacitors, two second resonance inductors, two second resonance capacitors, two transformers, a secondary rectification circuit, an output filter capacitor and an output load. A hybrid control mode of frequency conversion and phase shift is employed to achieve wide voltage gain in a wide load condition. The second resonance capacitors and the second resonance inductors are connected in series to obtain adjustable equivalent excitation inductance, the equivalent excitation inductance is smaller to facilitate achieving of the high voltage gain at a low frequency, and the equivalent excitation inductance is larger to facilitate improvement of the working efficiency at a high frequency. The maximum switching frequency isa resonant frequency, the phase between the two modules is regulated at this frequency to further widen the voltage gain so as to ensure the zero-voltage turning-on of a primary switch tube and the zero-current turning-off of a secondary rectification tube in the whole working range and facilitate achievement of high efficiency and high power density.

A multilayer capacitor comprises a multilayer body and a plurality of terminal electrodes formed on a side face of the multilayer body. The multilayer body includes an inner layer portion in which a plurality of dielectric layers and a plurality of inner electrodes are alternately laminated, and an outer layer portion in which a plurality of dielectric layers are laminated. In the outer layer portion, a conduction path electrically connecting a plurality of different positions in at least one of the plurality of terminal electrodes to each other is arranged. A current flowing through the terminal electrode electrically connected to the conduction path is shunted into the conduction path. This lowers the equivalent series inductance of the multilayer capacitor.