210results about How to "Reduce common mode noise" patented technology

A multilayer feedthrough capacitor having a first internal conductor arranged in a dielectric body, an intermediate internal conductor arranged in the dielectric body and stacked with the first internal conductor via a ceramic layer, a second internal conductor arranged in the dielectric body and stacked with the intermediate internal conductor via a ceramic layer, a first terminal electrode formed at an outside surface of the dielectric body and connected to the first internal conductor, a second terminal electrode formed at the outside surface of the dielectric body and connected to the second internal conductor, and an intermediate terminal electrode formed at the outside surface of the dielectric body and connected to the intermediate internal conductor. The intermediate terminal electrode is connected to the ground, while the first terminal electrode and the second terminal electrode are connected to paths for transmitting signals. The first internal conductor and the second internal conductor have currents flowing through them in opposite directions.

A power supply apparatus for electric operation is provided for an electric operation apparatus, and includes an instructing signal input portion which generates a DC output voltage to a high-frequency generating circuit that generates a high frequency and which receives an instructing signal for controlling the output voltage. The instructing signal input portion includes at least a noise reducing circuit which reduces a normal-mode noise.

A bridgeless power factor correction converter that can reduce common-mode noise and enhance power density is made up of a boost inductor coupled to an input end, a bidirectional switch connected in series with the boost inductor, a first series rectifying circuit having a junction node connected between the boost inductor and the bi-directional switch, a second series rectifying circuit connected in parallel with the first series rectifying circuit and having a junction node coupled to the bi-directional switch, and an output capacitor connected in parallel with the second series rectifying circuit, in which the second series rectifying circuit is made up of slow-recovery diodes and the first series rectifying circuit is made up of fast-recovery diodes.

A double reference wave modulation scheme for filterless power amplifiers is disclosed for reducing EMI and common mode voltages. In the filterless power amplifier, differential outputs for driving load impedance are feedback and corrected based on input audio signals. Reference wave generators generate reference waves. A control logic results pulses in the pair of differential outputs in response to a clock signal or a reference voltage and a cross relationship between the input audio signal and the first and second reference waves. Pulses of one of the differential outputs are not overlapped with pulses of the other of the differential outputs for eliminating common mode noises of the power amplifier.

A method and apparatus for reducing common mode noise in a three phase pulse width modulated (PWM) system the method comprising the steps of receiving modulating waveforms, identifying a first of the modulating waveforms that is instantaneously the maximum of the modulating waveforms, identifying a second of the modulating waveforms that is instantaneously the minimum of the modulating waveforms, for a first phase associated with at least one of the first and second identified waveforms, substituting a first substitute waveform for the one of the first and second waveforms, for the first phase, modifying at least one of the first substituted waveform and duty cycle signals generated by comparing the first substituted waveform with the carrier signal as a function of a first rule set to substantially minimize the effects of turn on delays and for at least one of the second and third phases, modifying at least one of the associated modulating waveform and duty cycle signals generated by comparing the modulating waveform with the carrier signal as a function of a second rule set to substantially eliminate the effects of turn on delays where the second rule set is different than the first rule set.

An apparatus and method for reducing common mode noise capacitive coupling from a primary winding to a secondary winding in a transformer. In an embodiment, the primary winding has two terminals and a plurality of coil turns therebetween formed by a plurality of PCB layers sandwiched together, each having at least one of the coil turns formed thereon. The coils turns are connected in a predetermined way to form the primary winding. One terminal of the primary winding is connected to a coil turn on a first one of the PCB layers, and the other terminal is connected to a coil turn on a second one of the PCB layers. The PCB layers are stacked to form the primary winding. The secondary winding or windings are positioned adjacent to a selected one of the stacked PCB layers that is in a position between the first and second PCB layers.

We describe a switch mode power supply having a power input, a switch, a transformer, and a power output. The transformer has a primary winding coupled to said power input via said switch, and a secondary winding coupled to said power output. The transformer further comprises an auxiliary winding and a coupling structure capacitatively coupled to said secondary winding of said transformer; wherein said coupling structure does not comprise a shield or screen between said primary and secondary windings. The switch mode power supply further comprises a coupling capacitor connected between said coupling structure and said auxiliary winding to provide a noise suppression voltage from said auxiliary winding to said secondary winding to at least partially cancel a common mode noise voltage on said secondary winding from unshielded coupling from said primary winding.

A layout method for the creation of a differential pair for the transmission of signals generates a differential pair between a differential signal sender and a differential signal receiver in a layout of a PCB. Differential signals are transmitted via two wires. A plurality of vertical lines are created on the differential pair. Junctions of the vertical lines and the two wires are defined as pairs of points. A first length between one terminal of the differential signal sender and one point of each pair of points and a second length between the other terminal of the differential signal sender and the other point of each pair of points are calculated. If any difference between the first length and the second length does not fall within an allowable range, the lengths of the two wires are adjusted.