The invention discloses a method for inhibiting common-mode
voltage in SVPWM (
Space Vector Pulse Width Modulation) modulation of a three-phase two-level
inverter, which comprises the following steps of: obtaining expected d-q shafting
voltage Udref and Uqref through a
current loop, and obtaining an included angle theta between a d axis and an alpha axis through a motor position or a speed sensor; according to the Udref, the Uqref and the theta, calculating to obtain an expected reference
voltage vector amplitude Usref and an included angle between the Usref and the alpha axis, judging a sector S where the Usref is located according to the included angle, and looking up a table according to the sector S to obtain three unit vectors Ux, Uy and Uz which need to be used and have a fixed action sequence; according to the
volt-second balance principle, the action time Tx, Ty and Tz of the unit vectors Ux, Uy and Uz is obtained through calculation, and Tult is calculated; the part of Ty is eliminated, the part of Tmin is eliminated, Ty is made to be equal to Tmin, and Tmin is
dead time; and SVPWM output is carried out by adopting a decreasing symmetric five-section mode. Under the condition that hardware cost is not increased, the problem that + / -Udc / 2 peaks appear in common-mode voltage in PWM modulation can be effectively suppressed, and the problem that a motor bearing is damaged by higher
harmonics of three-phase current is obviously solved.