Three-level zero common-mode voltage modulation method based on DSP (digital signal processor) and CPLD (complex programmable logic device)

A technology of common-mode voltage and modulation method, which is applied in the field of three-level zero-common-mode voltage modulation, and can solve problems such as failure to fundamentally eliminate common-mode voltage

Inactive Publication Date: 2012-10-17
HEFEI UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

These methods can suppress the common-mode voltage to varying degrees

Method used

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  • Three-level zero common-mode voltage modulation method based on DSP (digital signal processor) and CPLD (complex programmable logic device)
  • Three-level zero common-mode voltage modulation method based on DSP (digital signal processor) and CPLD (complex programmable logic device)
  • Three-level zero common-mode voltage modulation method based on DSP (digital signal processor) and CPLD (complex programmable logic device)

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Embodiment Construction

[0066] Such as Figure 7 Shown, a kind of three-level zero-common-mode voltage modulation method based on DSP and CPLD comprises the following steps:

[0067] (1) Use DSP1 to perform two-level modulation to modulate two complementary 6-channel two-level PWM signals, and mark the signals as EPWM1 ​​to EPWM6, where EPWM1 ​​and EPWM2 are complementary, EPWM3 and EPWM4 are complementary, and EPWM5 and EPWM6 are complementary;

[0068] (2) Transfer the 6 two-level PWM signals generated by DSP1 to CPLD2 through external pins, and CPLD2 adjusts the 6 two-level PWM signals to generate 12 PWM signals, and mark the 12 signals respectively For PWM1 to PWM12;

[0069] Assign values ​​to PWM1-PWM4: When the EPWM1 ​​and EPWM3 signals generated by DSP1 in step (1) are not at low level at the same time, implement the following distribution method: PWM1 takes the signal of EPWM4, PWM2 takes the signal of EPWM1, and PWM3 takes the signal of EPWM3 Signal, PWM4 takes the signal of EPWM2; when t...

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Abstract

The invention discloses a three-level zero common-mode voltage modulation method based on a DSP (digital signal processor) and a CPLD (complex programmable logic device). PWM (pulse-width modulation) pulse wave modulated by two levels is distributed and adjusted to produce a group of median vector on-off states effective for a three-level inverter, and three-level median vector combination is directly adopted for directly controlling a three-level main circuit to achieve the purpose that the output common-mode voltage is zero. The modulation method is simple and easy to implement without any additional hardware circuits, and applicable to any modulation wave. All output common-mode voltages are zero so as to eliminate leakage current caused by common-mode voltage and drain capacitance, and fundamentally eliminate the common-mode voltage.

Description

technical field [0001] The invention relates to a three-level zero-common-mode voltage modulation method, in particular to a three-level zero-common-mode voltage modulation method based on DSP and CPLD. Background technique [0002] With the rapid development of power electronics and computer technology, inverters are widely used in high-power fields. Especially with the continuous improvement and perfection of the three-level technology, the three-level inverter has become a dominant position in high-power applications. Compared with the traditional two-level converter, the three-level converter has the advantages of high withstand voltage, low switching loss, and low output harmonics, and shows obvious advantages in high-voltage and high-power applications, so it has caused people's attention. However, there is a common mode voltage problem in the three-level converter. Due to the existence of the common mode voltage, an uncontrollable leakage current is generated throu...

Claims

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Application Information

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IPC IPC(8): H02M7/487H02M1/088
CPCH02M7/487H02M7/5395H02M1/123
Inventor 王付胜张兴何立灿李飞刘淳刘芳
Owner HEFEI UNIV OF TECH
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