5results about How to "Reduce common mode voltage" patented technology

This application relates to a common-mode voltage suppression method based on cascaded observers, specifically for high-precision motor drives. The aim is to address the shortcomings of existing CMV suppression methods, which rely heavily on experience and suffer from low robustness. This method utilizes cascaded observers to observe and compensate for the total disturbance in the motor control system, calculating a reference voltage vector. A discrete virtual vector set is constructed, and the vector plane formed by this set is divided into multiple continuous and non-overlapping sub-regions, ensuring that each sub-region uniquely corresponds to a virtual vector in the discrete virtual vector set. The sub-region to which the reference voltage vector belongs in the vector plane is determined, and the virtual vector corresponding to that sub-region is used as the target vector. A PWM signal is generated based on the target vector to control the motor, achieving common-mode voltage suppression. This application demonstrates significant suppression effects on the first, second, and sixth harmonics, reducing the common-mode voltage to one-third of that achieved by traditional methods, while effectively reducing computation time.

The invention discloses a low-power-consumption high-speed two-stage dynamic comparator for an analog-to-digital converter, relates to the technical field of integrated circuits, and aims to solve the problems that a traditional dynamic comparator is high in power consumption, limited in speed and uncontrollable in balance between offset voltage and performance. The comparator comprises a two-stage dynamic structure of a pre-amplification stage and a latch stage, wherein the pre-amplification stage takes a PMOS transistor as an input tube and is matched with an NMOS switching tube and a PMOS active load tube to realize preliminary amplification of an input differential signal; the latch stage adopts a PMOS latch structure instead of a traditional NMOS latch structure. And through two paths of delay controllable clock signals (clkb1 and clkb2), the latch stage is controlled to be activated in a delayed manner after the preamplifier stage works for a preset time, and meanwhile, a current source of the preamplifier stage is closed when the latch stage is activated. By adjusting latch level delay time, offset voltage, power consumption and speed can be flexibly balanced, performance requirements of different analog-to-digital converters are met, and the analog-to-digital converter is suitable for scenes such as portable equipment, communication systems and the like with high requirements on energy efficiency and speed.

This invention discloses a method for interphase battery charge balancing in a three-phase cascaded H-bridge based on model predictive control. A simulation circuit model of a 7-level cascaded H-bridge grid-connected inverter based on model predictive control was built in Matlab / Simulink simulation software, and the simulation results were recorded. The DC-side voltage vo of each H-bridge unit of the inverter is specified. dc The value is 150V, and the mains voltage is v. g The values ​​are set to 220V, the fundamental frequency to 50Hz, the sampling time T for model predictive control to 0.1ms, the grid-connected filter inductor L to 1mH, and the equivalent resistance R of the grid-connected filter inductor to 0.1Ω. The SOC is set... a =70.1%, SOC b =70%, SOC c =69.9%, ε=0.01, the grid-connected filter inductor L is 1mH, the equivalent resistance R of the grid-connected filter inductor is 0.1Ω, the grid-connected current is controlled by model predictive control, and a reward function is introduced to select redundant voltage vectors to balance the phase SoC without affecting the current performance. After the error of the SoC is less than a certain given value, the SoC balancing is stopped to achieve the minimum common mode voltage.

The application discloses a 4MV modulation method for inhibiting common-mode current of a photovoltaic ANPC type three-level inverter, and steps of the method comprise the following steps: 1. applying Kirchhoff's law to deduce a relationship formula of common-mode voltage and a parasitic capacitance of a photovoltaic array, and establishing a common-mode equivalent circuit; 2. deducing a functional relationship formula of instantaneous values of a neutral current, three-phase currents and a switch state; 3. according to a relationship between a basic vector diagram and a midpoint current expression and a principle that the common-mode voltage is 0, selecting six middle vectors as basic vectors, and using four middle vectors to synthesize a reference voltage vector in each sector, wherein two middle vectors are used for synthesizing the reference voltage vector, and the other two middle vectors are used as equivalent zero vectors and are used for introducing the neutral current to effectively reduce fluctuation of a midpoint potential. The application replaces the zero vectors with a pair of equal-amplitude and opposite-phase middle vectors, can reduce deviation of the midpoint potential, further reduces common-mode voltage caused by the deviation of the midpoint potential, and thus can reduce the common-mode current of the system.

The invention provides a multi-level power converter fault tolerance method, which comprises the following steps of: acquiring an output voltage, an inverter side current and a direct current side voltage, performing conversion, and performing PI modulation to obtain a modulation wave of a system; judging whether the system has a fault or not, and judging a specific fault-tolerant scheme according to the modulation degree of the modulation wave if the system has the fault; based on a fault-tolerant scheme, selecting an output state of a redundant vector of a non-fault phase; and based on the selected output state, generating a corresponding driving signal through carrier phase-shifting PWM (Pulse-Width Modulation). The multi-level hybrid topology can keep the same working state before and after the fault, the floating capacitor voltage and the direct current side capacitor voltage are stable, the fault response is rapid, the large-range fluctuation of the output voltage and the output current is avoided, the smooth switching of the working modes is ensured, and the fault tolerance of the system is improved.